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functional block diagram rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adsp-2100 family dsp microcomputers adsp-21xx summary 16-bit fixed-point dsp microprocessors with on-chip memory enhanced harvard architecture for three-bus performance: instruction bus & dual data buses independent computation units: alu, multiplier/ accumulator, and shifter single-cycle instruction execution & multifunction instructions on-chip program memory ram or rom & data memory ram integrated i/o peripherals: serial ports, timer, host interface port (adsp-2111 only) features 25 mips, 40 ns maximum instruction rate separate on-chip buses for program and data memory program memory stores both instructions and data (three-bus performance) dual data address generators with modulo and bit-reverse addressing efficient program sequencing with zero-overhead looping: single-cycle loop setup automatic booting of on-chip program memory from byte-wide external memory (e.g., eprom ) double-buffered serial ports with companding hardware, automatic data buffering, and multichannel operation adsp-2111 host interface port provides easy interface to 68000, 80c51, adsp-21xx, etc. automatic booting of adsp-2111 program memory through host interface port three edge- or level-sensitive interrupts low power idle instruction pga, plcc, pqfp, and tqfp packages mil-std-883b versions available this data sheet describes the following adsp-2100 family processors: adsp-2101 adsp-2103 3.3 v version of adsp-2101 adsp-2105 low cost dsp adsp-2111 dsp with host interface port adsp-2115 adsp-2161/62/63/64 custom rom-programmed dsps the following adsp-2100 family processors are not included in this data sheet: ADSP-2100A dsp microprocessor adsp-2165/66 rom-programmed adsp-216x processors with powerdown and larger on-chip memories (12k program memory rom, 1k program memory ram, 4k data memory ram) adsp-21msp5x mixed-signal dsp processors with integrated on-chip a/d and d/a plus powerdown adsp-2171 speed and feature enhanced adsp-2100 family processor with host interface port, powerdown, and instruction set extensions for bit manipulation, multiplication, biased rounding, and global interrupt masking adsp-2181 adsp-21xx processor with adsp-2171 features plus 80k bytes of on-chip ram configured as 16k words of program memory and 16k words of data memory. refer to the individual data sheet of each of these processors for further information. general description the adsp-2100 family processors are single-chip micro- computers optimized for digital signal processing (dsp) and other high speed numeric processing applications. the adsp-21xx processors are all built upon a common core. each processor combines the core dsp architecturecomputation units, data address generators, and program sequencerwith differentiating features such as on-chip program and data memory ram, a programmable timer, one or two serial ports, and, on the adsp-2111, a host interface port. external address bus data memory program memory external data bus adsp-2100 core arithmetic units shifter mac alu memory serial ports sport 0 sport 1 host interface port (adsp-2111) flags (adsp-2111) data address generators dag 1 dag 2 program sequencer program memory address data memory address program memory data data memory data timer ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703
adsp-21xx C2C rev. b fabricated in a high speed, submicron, double-layer metal cmos process, the highest-performance adsp-21xx proces- sors operate at 25 mhz with a 40 ns instruction cycle time. every instruction can execute in a single cycle. fabrication in cmos results in low power dissipation. the adsp-2100 familys flexible architecture and compre- hensive instruction set support a high degree of parallelism. in one cycle the adsp-21xx can perform all of the following operations: ? generate the next program address ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computation ? receive and transmit data via one or two serial ports ? receive and/or transmit data via the host interface port (adsp-2111 only) the adsp-2101, adsp-2105, and adsp-2115 comprise the basic set of processors of the family. each of these three devices contains program and data memory ram, an interval timer, and one or two serial ports. the adsp-2103 is a 3.3 volt power supply version of the adsp-2101; it is identical to the adsp-2101 in all other characteristics. table i shows the features of each adsp-21xx processor. the adsp-2111 adds a 16-bit host interface port (hip) to the basic set of adsp-21xx integrated features. the host port provides a simple interface to host microprocessors or microcontrollers such as the 8031, 68000, or isa bus. table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . 1 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 architecture overview . . . . . . . . . . . . . . . . . . . . 4 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 host interface port (adsp-2111) . . . . . . . . . . . . . . . . . . . . 6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 program memory interface . . . . . . . . . . . . . . . . . . . . . . . . 10 program memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 data memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 boot memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 low power idle instruction . . . . . . . . . . . . . . . . . . . . . . 13 adsp-216x prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ordering procedure for adsp-216x rom processors . . . . 13 wafer products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 functional differences for older revision devices . . . . . . 14 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 specifications (adsp-2101/2105/2115/2161/2163) . . . . . . . . . . . . . . . 17 recommended operating conditions . . . . . . . . . . . . . . . . 17 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 17 supply current & power (adsp-2101/2161/2163) . . . . . . 18 power dissipation example . . . . . . . . . . . . . . . . . . . . . . . . 19 environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . . 19 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 specifications (adsp-2111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 recommended operating conditions . . . . . . . . . . . . . . . . 21 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21 supply current & power . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power dissipation example . . . . . . . . . . . . . . . . . . . . . . . . 23 environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . . 23 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 specifications (adsp-2103/2162/2164) . . . . . . . . . 25 recommended operating conditions . . . . . . . . . . . . . . . . 25 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25 supply current & power . . . . . . . . . . . . . . . . . . . . . . . . . . 26 power dissipation example . . . . . . . . . . . . . . . . . . . . . . . . 27 environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . . 27 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 timing parameters (adsp-2101/2105/2111/2115/2161/2163) . . . . . . . . . . . . 29 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 interrupts & flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 bus requestCbus grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 memory write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 host interface port (adsp-2111) . . . . . . . . . . . . . . . . . . . 36 timing parameters (adsp-2103/2162/2164) . . . . 44 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 interrupts & flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 bus requestCbus grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 memory write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 pin configurations 68-pin pga (adsp-2101) . . . . . . . . . . . . . . . . . . . . . . . . 51 68-lead plcc (adsp-2101/2103/2105/2115/216x) . . . . 52 80-lead pqfp (adsp-2101/2103/2115/216x) . . . . . . . . . 53 80-lead tqfp (adsp-2115) . . . . . . . . . . . . . . . . . . . . . . 53 100-pin pga (adsp-2111) . . . . . . . . . . . . . . . . . . . . . . . 54 100-lead pqfp (adsp-2111) . . . . . . . . . . . . . . . . . . . . . 55 package outline dimensions 68-pin pga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 68-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 80-lead pqfp, 80-lead tqfp . . . . . . . . . . . . . . . . . . . . 58 1 00-pin pga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 100-lead pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . 61-62
adsp-21xx rev. b C3C table i. adsp-21xx processor features feature 2101 2103 2105 2115 2111 data memory (ram) 1k 1k 1 M 2 k 1 M 2 k1k program memory (ram) 2k 2k 1k 1k 2k timer ????? serial port 0 (multichannel) ?? C ?? serial port 1 ????? host interface port C C C C ? speed grades (instruction cycle time) 10.24 mhz (76.9 ns) C ? C C C 13.0 mhz (76.9 ns) C C C C ? 13.824 mhz (72.3 ns) C C ? C C 16.67 mhz (60 ns) ? C C ?? 20.0 mhz (50 ns) ? C ??? 25 mhz (40 ns) ? C C ? C supply voltage 5 v 3.3 v 5 v 5 v 5 v packages 68-pin pga ? C C C C 68-lead plcc ???? C 80-lead pqfp ?? C ? C 80-lead tqfp C C C ? C 100-pin pga C C C C ? 100-lead pqfp C C C C ? temperature grades k commercial 0 c to +70 c ????? b industrial C40 c to +85 c ????? t extended C55 c to +125 c ? C C C ? table ii. adsp-216x rom-programmed processor features feature 2161 2162 2163 2164 data memory (ram) 1 M 2 k 1 M 2 k 1 M 2 k 1 M 2 k program memory (rom) 8k 8k 4k 4k program memory (ram) C C C C timer ???? serial port 0 (multichannel) ???? serial port 1 ???? supply voltage 5 v 3.3 v 5 v 3.3 v speed grades (instruction cycle time) 10.24 mhz (97.6 ns) C ? C ? 16.67 mhz (60 ns) ? C ? C 25 mhz (40 ns) CC ? C packages 68-lead plcc ???? 80-lead pqfp ???? temperature grades k commercial 0 c to +70 c ???? b industrial C40 c to +85 c ????
adsp-21xx C4C rev. b the adsp-216x series are memory-variant versions of the adsp-2101 and adsp-2103 that contain factory-programmed on-chip rom program memory. these devices offer different amounts of on-chip memory for program and data storage. table ii shows the features available in the adsp-216x series of custom rom-coded processors. the adsp-216x products eliminate the need for an external boot eprom in your system, and can also eliminate the need for any external program memory by fitting the entire applica- tion program in on-chip rom. these devices thus provide an excellent option for volume applications where board space and system cost constraints are of critical concern. development tools the adsp-21xx processors are supported by a complete set of tools for system development. the adsp-2100 family devel- opment software includes c and assembly language tools that allow programmers to write code for any of the adsp-21xx processors. the ansi c compiler generates adsp-21xx assembly source code, while the runtime c library provides ansi-standard and custom dsp library routines. the adsp- 21xx assembler produces object code modules which the linker combines into an executable file. the processor simulators provide an interactive instruction-level simulation with a reconfigurable, windowed user interface. a prom splitter utility generates prom programmer compatible files. ez-ice ? in-circuit emulators allow debugging of adsp-21xx systems by providing a full range of emulation functions such as modification of memory and register values and execution breakpoints. ez-lab ? demonstration boards are complete dsp systems that execute eprom-based programs. the ez-kit lite is a very low-cost evaluation/development platform that contains both the hardware and software needed to evaluate the adsp-21xx architecture. additional details and ordering information is available in the adsp-2100 family software & hardware development tools data sheet (adds-21xx-tools). this data sheet can be requested from any analog devices sales office or distributor. additional information this data sheet provides a general overview of adsp-21xx processor functionality. for detailed design information on the architecture and instruction set, refer to the adsp-2100 family users manual , available from analog devices. architecture overview figure 1 shows a block diagram of the adsp-21xx architecture. the processors contain three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add, and multiply/subtract operations. the shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. the shifter can be used to efficiently implement numeric format control including multiword floating-point representations. the internal result (r) bus directly connects the computational units so that the output of any unit may be used as the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient use of these computational units. the sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. with internal loop counters and loop stacks, the adsp-21xx executes looped code with zero overheadno explicit jump instructions are required to maintain the loop. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. the circular buffering feature is also used by the serial ports for automatic data transfers to (and from) on- chip memory. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma, dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd, dmd) share a single external data bus. the bms , dms , and pms signals indicate which memory space is using the external buses. program memory can store both instructions and data, permit- ting the adsp-21xx to fetch two operands in a single cycle, one from program memory and one from data memory. the processor can fetch an operand from on-chip program memory and the next instruction in the same cycle. the memory interface supports slow memories and memory- mapped peripherals with programmable wait state generation. external devices can gain control of the processors buses with the use of the bus request/grant signals ( br , bg ). ez-ice and ez-lab are registered trademarks of analog devices, inc.
adsp-21xx rev. b C5C figure 1. adsp-21xx block diagram one bus grant execution mode (go mode) allows the adsp- 21xx to continue running from internal memory. a second execution mode requires the processor to halt while buses are granted. each adsp-21xx processor can respond to several different interrupts. there can be up to three external interrupts, configured as edge- or level-sensitive. internal interrupts can be generated by the timer, serial ports, and, on the adsp-2111, the host interface port. there is also a master reset signal. booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. after reset, three wait states are automatically generated. this allows, for example, a 60 ns adsp-2101 to use a 200 ns eprom as external boot memory. multiple programs can be selected and loaded from the eprom with no additional hardware. the data receive and transmit pins on sport1 (serial port 1) can be alternatively configured as a general-purpose input flag and output flag. you can use these pins for event signalling to and from an external device. the adsp-2111 has three additional flag outputs whose states are controlled through software. a programmable interval timer can generate periodic interrupts. a 16-bit count register (tcount) is decremented every n cycles, where nC1 is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the adsp-21xx processors include two synchronous serial ports (sports) for serial communications and multiproces- sor communication. all of the adsp-21xx processors have two serial ports (sport0, sport1) except for the adsp-2105, which has only sport1. the serial ports provide a complete synchronous serial interface with optional companding in hardware. a wide variety of framed or frameless data transmit and receive modes of opera- tion are available. each sport can generate an internal programmable serial clock or accept an external serial clock. each serial port has a 5-pin interface consisting of the following signals: signal name function sclk serial clock (i/o) rfs receive frame synchronization (i/o) tfs transmit frame synchronization (i/o) dr serial data receive dt serial data transmit the adsp-21xx serial ports offer the following capabilities: bidirectional each sport has a separate, double-buffered transmit and receive function. flexible clocking each sport can use an external serial clock or generate its own clock internally. r bus 16 dmd bus host port control pmd bus dma bus pma bus 14 24 16 external address bus external data bus host port data boot address generator timer 14 11 bus exchange companding circuitry 5 16 24 receive reg transmit reg serial port 1 external host port bus dma bus pma bus dmd bus pmd bus host interface port (adsp-2111 only) flags (adsp-2111 only) 3 program sequencer instruction register program memory sram or rom data memory sram data address generator #2 data address generator #1 14 input regs output regs shifter input regs output regs mac input regs output regs alu receive reg transmit reg serial port 0 (not on adsp-2105) 5 16 mux 24 mux
adsp-21xx C6C rev. b of the adsp-2111. the two status registers provide status information to both the adsp-2111 and the host processor. hsr7 contains a software reset bit which can be set by both the adsp-2111 and the host. hip transfers can be managed using either interrupts or polling. the hip generates an interrupt whenever an hdr register receives data from a host processor write. it also generates an interrupt when the host processor has performed a successful read of any hdr. the read/write status of the hdrs is also stored in the hsr registers. the hmask register bits can be used to mask the generation of read or write interrupts from individual hdr registers. bits in the imask register enable and disable all hip read interrupts or all hip write interrupts. so, for example, a write to hdr4 will cause an interrupt only if both the hdr4 write bit in hmask and the hip write interrupt enable bit in imask are set. the hip provides a second method of booting the adsp-2111 in which the host processor loads instructions into the hip. the adsp-2111 automatically transfers the data, in this case opcodes, to internal program memory. the bmode pin determines whether the adsp-2111 boots from the host processor through the hip or from external eprom over the data bus. interrupts the adsp-21xxs interrupt controller lets the processor respond to interrupts with a minimum of overhead. up to three external interrupt input pins, irq0 , irq1 , and irq2 , are provided. irq2 is always available as a dedicated pin; irq1 and irq0 may be alternately configured as part of serial port 1. the adsp-21xx also supports internal interrupts from the timer, the serial ports, and the host interface port (on the adsp-2111). the interrupts are internally prioritized and individually maskable (except for reset which is non-maskable). the irqx input pins can be programmed for either level- or edge- sensitivity. the interrupt priorities for each adsp-21xx processor are shown in table iii. the adsp-21xx uses a vectored interrupt scheme: when an interrupt is acknowledged, the processor shifts program control to the interrupt vector address corresponding to the interrupt received. interrupts can be optionally nested so that a higher priority interrupt can preempt the currently executing interrupt service routine. each interrupt vector location is four instruc- tions in length so that simple service routines can be coded entirely in this space. longer service routines require an additional jump or call instruction. individual interrupt requests are logically anded with the bits in the imask register; the highest-priority unmasked interrupt is then selected. the interrupt control register, icntl, allows the external interrupts to be set as either edge- or level-sensitive. depending on bit 4 in icntl, interrupt service routines can either be nested (with higher priority interrupts taking precedence) or be processed sequentially (with only one interrupt service active at a time). flexible framing the sports have independent framing for the transmit and receive functions; each function can run in a frameless mode or with frame synchronization signals inter- nally generated or externally generated; frame sync signals may be active high or inverted, with either of two pulse widths and timings. different word lengths each sport supports serial data word lengths from 3 to 16 bits. companding in hardware each sport provides optional a-law and m -law companding according to ccitt recommen- dation g.711. flexible interrupt scheme receive and transmit functions can generate a unique interrupt upon completion of a data word transfer. autobuffering with single-cycle overhead each sport can automatically receive or transmit the contents of an entire circular data buffer with only one overhead cycle per data word; an interrupt is generated after the transfer of the entire buffer is completed. multichannel capability (sport0 only) sport0 provides a multichannel interface to selectively receive or transmit a 24-word or 32-word, time-division multiplexed serial bit stream; this feature is especially useful for t1 or cept interfaces, or as a network communication scheme for multiple processors. (note that the adsp-2105 includes only sport1, not sport0, and thus does not offer multichannel operation.) alternate configuration sport1 can be alternatively configured as two external interrupt inputs ( irq0 , irq1 ) and the flag in and flag out signals (fi, fo). host interface port (adsp-2111) the adsp-2111 includes a host interface port (hip), a parallel i/o port that allows easy connection to a host processor. through the hip, the adsp-2111 can be accessed by the host processor as a memory-mapped peripheral. the host interface port can be thought of as an area of dual-ported memory, or mailbox registers, that allows communication between the computational core of the adsp-2111 and the host computer. the host interface port is completely asynchronous. the host processor can write data into the hip while the adsp-2111 is operating at full speed. three pins configure the hip for operation with different types of host processors. the hsize pin configures hip for 8- or 16- bit communication with the host processor. hmd0 configures the bus strobes, selecting either separate read and write strobes or a single read/write select and a host data strobe. hmd1 selects either separate address (3-bit) and data (16-bit) buses or a multiplexed 16-bit address/data bus with address latch enable. tying these pins to appropriate values configures the adsp- 2111 for straight-wire interface to a variety of industry-standard microprocessors and microcomputers. the hip contains six data registers (hdr5-0) and two status registers (hsr7-6) with an associated hmask register for masking interrupts from individual hip data registers. the hip data registers are memory-mapped in the internal data memory
adsp-21xx rev. b C7C the interrupt force and clear register, ifc, is a write-only register that contains a force bit and a clear bit for each inter- rupt (except for level-sensitive interrupts and the adsp-2111 hip interruptsthese cannot be forced or cleared in software). when responding to an interrupt, the astat, mstat, and imask status registers are pushed onto the status stack and the pc counter is loaded with the appropriate vector address. the status stack is seven levels deep (nine levels deep on the adsp-2111) to allow interrupt nesting. the stack is automati- cally popped when a return from the interrupt instruction is executed. pin definitions table iv (on next page) shows pin definitions for the adsp- 21xx processors. any inputs not used must be tied to v dd . table iii. interrupt vector addresses & priority adsp-2105 interrupt interrupt source vector address reset startup 0x0000 irq2 0x0004 (high priority) sport1 transmit or irq1 0x0010 sport1 receive or irq0 0x0014 timer 0x0018 (low priority) adsp-2101/2103/2115/216x interrupt interrupt source vector address reset startup 0x0000 irq2 0x0004 (high priority) sport0 transmit 0x0008 sport0 receive 0x000c sport1 transmit or irq1 0x0010 sport1 receive or irq0 0x0014 timer 0x0018 (low priority) adsp-2111 interrupt interrupt source vector address reset startup 0x0000 irq2 0x0004 (high priority) hip write from host 0x0008 hip read to host 0x000c sport0 transmit 0x0010 sport0 receive 0x0014 sport1 transmit or irq1 0x0018 sport1 receive or irq0 0x001c timer 0x0020 (low priority) system interface figure 3 shows a typical system for the adsp-2101, adsp- 2115, or adsp-2103, with two serial i/o devices, a boot eprom, and optional external program and data memory. a total of 15k words of data memory and 16k words of program memory is addressable for the adsp-2101 and adsp-2103. a total of 14.5k words of data memory and 15k words of program memory is addressable for the adsp-2115. figure 4 shows a system diagram for the adsp-2105, with one serial i/o device, a boot eprom, and optional external program and data memory. a total of 14.5k words of data memory and 15k words of program memory is addressable for the adsp-2105. figure 5 shows a system diagram for the adsp-2111, with two serial i/o devices, a host processor, a boot eprom, and optional external program and data memory. a total of 15k words of data memory and 16k words of program memory is addressable. programmable wait-state generation allows the processors to easily interface to slow external memories. the adsp-2101, adsp-2103, adsp-2115, and adsp-2111 processors also provide either: one external interrupt ( irq2 ) and two serial ports (sport0, sport1), or three external interrupts ( irq2 , irq1 , irq0 ) and one serial port (sport0). the adsp-2105 provides either: one external interrupt ( irq2 ) and one serial port (sport1), or three external interrupts ( irq2 , irq1 , irq0 ) with no serial port. clock signals the adsp-21xx processors clkin input may be driven by a crystal or by a ttl-compatible external clock signal. the clkin input may not be halted or changed in frequency during operation, nor operated below the specified low frequency limit. if an external clock is used, it should be a ttl-compatible signal running at the instruction rate. the signal should be connected to the processors clkin input; in this case, the xtal input must be left unconnected. because the adsp-21xx processors include an on-chip oscilla- tor circuit, an external crystal may also be used. the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 2. a parallel- resonant, fundamental frequency, microprocessor-grade crystal should be used. figure 2. external crystal connections clkin clkout xtal adsp-21xx
adsp-21xx C8C rev. b a clock output signal (clkout) is generated by the processor, synchronized to the processors internal cycles. reset the reset signal initiates a complete reset of the adsp-21xx. the reset signal must be asserted when the chip is powered up to assure proper initialization. if the reset signal is applied during initial power-up, it must be held long enough to allow the processors internal clock to stabilize. if reset is activated at any time after power-up and the input clock frequency does not change, the processors internal clock continues and does not require this stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 t ck cycles will ensure that the pll has locked (this does not, however, include the crystal oscillator start-up time). during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulse width specification, t rsp . to generate the reset signal, use either an rc circuit with an external schmidt trigger or a commercially available reset ic. (do not use only an rc circuit.) table iv. adsp-21xx pin definitions pin # of input / name(s) pins output function address 14 o address outputs for program, data and boot memory. data 1 24 i/o data i/o pins for program and data memories. input only for boot memory, with two msbs used for boot memory addresses. unused data lines may be left floating. reset 1 i processor reset input irq2 1 i external interrupt request #2 br 2 1 i external bus request input bg 1 o external bus grant output pms 1 o external program memory select dms 1 o external data memory select bms 1 o boot memory select rd 1 o external memory read enable wr 1 o external memory write enable mmap 1 i memory map select input clkin, xtal 2 i external clock or quartz crystal input clkout 1 o processor clock output v dd power supply pins gnd ground pins sport0 3 5 i/o serial port 0 pins (tfs0, rfs0, dt0, dr0, sclk0) sport1 5 i/o serial port 1 pins (tfs1, rfs1, dt1, dr1, sclk1) or interrupts & flags: irq0 (rfs1) 1 i external interrupt request #0 irq1 (tfs1) 1 i external interrupt request #1 fi (dr1) 1 i flag input pin fo (dt1) 1 o flag output pin fl2C0 (adsp-2111 only) 3 o general purpose flag output pins host interface port (adsp-2111 only) hsel 1 i hip select input hack 1 o hip acknowledge output hsize 1 i 8/16-bit host select (0 = 16-bit, 1 = 8-bit) bmode 1 i boot mode select (0 = standard eprom booting, 1 = hip booting) hmd0 1 i bus strobe select (0 = rd / wr , 1 = rw / ds ) hmd1 1 i hip address/data mode select (0 = separate, 1 = multiplexed) hrd /hrw 1 i hip read strobe or read/write select hwr / hds 1 i hip write strobe or host data strobe select hd15C0/had15-0 16 i/o hip data or hip data and address ha2/ale 1 i host address 2 input or address latch enable input ha1C0/unused 2 i host address 1 and 0 inputs notes 1 unused data bus lines may be left floating. 2 br must be tied high (to v dd ) if not used. 3 adsp-2105 does not have sport0. (sport0 pins are no connects on the adsp-2105.)
adsp-21xx rev. b C9C figure 4. adsp-2105 system figure 3. adsp-2101/adsp-2103/adsp-2115 system br bg clkin reset irq2 bms adsp-2101 or adsp-2103 or adsp-2115 clkout addr data (optional) 1x clock or crystal pms dms rd wr addr 13-0 data 23-0 addr data (optional) addr data boot memory e.g. eprom 2764 27128 27256 27512 program memory data memory & peripherals 14 24 d 23-22 a 13-0 d 15-8 d 23-0 d 23-8 a 13-0 a 13-0 xtal mmap serial device (optional) sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport 1 sclk0 rfs0 tfs0 dt0 dr0 sport 0 serial device (optional) oe we cs oe we cs oe cs the two msbs of the data bus (d 23-22 ) are used to supply the two msbs of the boot memory eprom address. this is only required for the 27256 and 27512. br bg clkin reset irq2 bms adsp-2105 clkout addr data (optional) 1x clock or crystal pms dms rd wr addr 13-0 data 23-0 addr data (optional) addr data boot memory e.g. eprom 2764 27128 27256 27512 program memory data memory & peripherals 14 24 d 23-22 a 13-0 d 15-8 d 23-0 d 23-8 a 13-0 a 13-0 xtal mmap serial device (optional) sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport 1 oe we cs oe we cs oe cs the two msbs of the data bus (d 23-22 ) are used to supply the two msbs of the boot memory eprom address. this is only required for the 27256 and 27512.
adsp-21xx C10C rev. b figure 5. adsp-2111 system the reset input resets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the mstat register. when reset is released, the boot loading sequence is performed (provided there is no pending bus request and the chip is configured for booting, with mmap = 0). the first instruction is then fetched from internal program memory location 0x0000. program memory interface the on-chip program memory address bus (pma) and on-chip program memory data bus (pmd) are multiplexed with the on- chip data memory buses (dma, dmd), creating a single external data bus and a single external address bus. the external data bus is bidirectional and is 24 bits wide to allow instruction fetches from external program memory. program memory may contain code and data. the external address bus is 14 bits wide. for the adsp-2101, adsp-2103, and adsp-2111, these lines can directly address up to 16k words, of which 2k are on-chip. for the adsp-2105 and adsp-2115, the address lines can directly address up to 15k words, of which 1k is on-chip. the data lines are bidirectional. the program memory select ( pms ) signal indicates accesses to program memory and can be used as a chip select signal. the write ( wr ) signal indicates a write operation and is used as a write strobe. the read ( rd ) signal indicates a read operation and is used as a read strobe or output enable signal. the adsp-21xx processors write data from their 16-bit registers to 24-bit program memory using the px register to provide the lower eight bits. when the processor reads 16-bit data from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the px register. the program memory interface can generate 0 to 7 wait states for external memory devices; default is to 7 wait states after reset . program memory maps program memory can be mapped in two ways, depending on the state of the mmap pin. figure 6 shows the two program memory maps for the adsp-2101, adsp-2103, and adsp-2111. figure 8 shows the program memory maps for the adsp-2105 and adsp-2115. figures 7 and 9 show the program memory maps for the adsp-2161/62 and adsp-2163/ 64, respectively. br bg clkin reset irq2 bms clkout addr data (optional) 1x clock or crystal pms dms rd wr addr 13-0 data 23-0 addr data (optional) addr data boot memory e.g. eprom 2764 27128 27256 27512 program memory data memory & peripherals 14 24 d 23-22 a 13-0 d 15-8 d 23-0 d 23-8 a 13-0 a 13-0 xtal mmap serial device (optional) sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport 1 sclk0 rfs0 tfs0 dt0 dr0 sport 0 serial device (optional) oe we cs oe we cs oe cs adsp-2111 host processor (optional) host interface port control data / addr (optional) fl0 fl1 fl2 7 16 the two msbs of the data bus (d 23-22 ) are used to supply the two msbs of the boot memory eprom address. this is only required for the 27256 and 27512.
adsp-21xx rev. b C11C adsp-2101/adsp-2103/adsp-2111 when mmap = 0, on-chip program memory ram occupies 2k words beginning at address 0x0000. off-chip program memory uses the remaining 14k words beginning at address 0x0800. in this configurationCwhen mmap = 0Cthe boot loading sequence (described below in boot memory inter- face) is automatically initiated when reset is released. when mmap = 1, 14k words of off-chip program memory begin at address 0x0000 and on-chip program memory ram is located in the upper 2k words, beginning at address 0x3800. in this configuration, program memory is not booted although it can be written to and read under program control. adsp-2105/adsp-2115 when mmap = 0, on-chip program memory ram occupies 1k words beginning at address 0x0000. off-chip program memory uses the remaining 14k words beginning at address 0x0800. in this configurationCwhen mmap = 0Cthe boot loading sequence (described below in boot memory inter- face) is automatically initiated when reset is released. when mmap = 1, 14k words of off-chip program memory begin at address 0x0000 and on-chip program memory ram is located in the 1k words between addresses 0x3800C0x3bff. in this configuration, program memory is not booted although it can be written to and read under program control. internal ram loaded from external boot memory external 0x07ff 0x0800 0x3fff 0x0000 external no booting 0x37ff 0x3800 0x3fff 0x0000 mmap=0 mmap=1 internal ram 2k 14k 2k 14k figure 6. adsp-2101/adsp-2103/adsp-2111 program memory maps figure 8. adsp-2105/adsp-2115 program memory maps figure 7. adsp-2161/62 program memory maps figure 9. adsp-2163/64 program memory maps 0x07ff 0x0800 0x1ff0 0x1fff 0x2000 0x1ff0 0x1fff 0x2000 mmap=0 0x3fff 0x0000 8k external 8k internal rom 0x0000 mmap=1 0x3fff 0x3800 0x37ff 2k external 6k internal rom 6k external 2k internal rom reserved reserved internal ram loaded from external boot memory external 0x03ff 0x0400 0x3fff 0x0000 external 0x3bff 0x3c00 0x3fff 0x0000 mmap=0 mmap=1 no booting 0x37ff 0x3800 0x07ff 0x0800 reserved 1k 14k 14k 1k internal ram 1k 1k reserved 4k internal rom 12k external 0x3fff 0x0000 2k external 0x3fff 0x0000 mmap=0 mmap=1 0x37ff 0x3800 2k internal rom 2k internal rom 10k external 0x07ff 0x0800 0x0ff0 0x0fff 0x1000 0x0ff0 reserved reserved 0x0fff 0x1000
adsp-21xx C12C rev. b all processors the remaining 14k of data memory is located off-chip. this external data memory is divided into five zones, each associated with its own wait-state generator. this allows slower peripherals to be memory-mapped into data memory for which wait states are specified. by mapping peripherals into different zones, you can accommodate peripherals with different wait-state require- ments. all zones default to seven wait states after reset . boot memory interface on the adsp-2101, adsp-2103, and adsp-2111, boot memory is an external 64k by 8 space, divided into eight separate 8k by 8 pages. on the adsp-2105 and adsp-2115, boot memory is a 32k by 8 space, divided into eight separate 4k by 8 pages. the 8-bit bytes are automatically packed into 24-bit instruction words by each processor, for loading into on- chip program memory. three bits in the processors system control register select which page is loaded by the boot memory interface. another bit in the system control register allows the forcing of a boot loading sequence under software control. boot loading from page 0 after reset is initiated automatically if mmap = 0. the boot memory interface can generate zero to seven wait states; it defaults to three wait states after reset . this allows the adsp-21xx to boot from a single low cost eprom such as a 27c256. program memory is booted one byte at a time and converted to 24-bit program memory words. the bms and rd signals are used to select and to strobe the boot memory interface. only 8-bit data is read over the data bus, on pins d8-d15. to accommodate up to eight pages of boot memory, the two msbs of the data bus are used in the boot memory interface as the two msbs of the boot memory address: d23, d22, and a13 supply the boot page number. the adsp-2100 family assembler and linker allow the creation of programs and data structures requiring multiple boot pages during execution. the br signal is recognized during the booting sequence. the bus is granted after loading the current byte is completed. br during booting may be used to implement booting under control of a host processor. bus interface the adsp-21xx processors can relinquish control of their data and address buses to an external device. when the external device requires control of the buses, it asserts the bus request signal ( br ). if the adsp-21xx is not performing an external memory access, it responds to the active br input in the next cycle by: ? three-stating the data and address buses and the pms , dms , bms , rd , wr output drivers, ? asserting the bus grant ( bg ) signal, ? and halting program execution. if the go mode is set, however, the adsp-21xx will not halt program execution until it encounters an instruction that requires an external memory access. data memory interface the data memory address bus (dma) is 14 bits wide. the bidirectional external data bus is 24 bits wide, with the upper 16 bits used for data memory data (dmd) transfers. the data memory select ( dms ) signal indicates access to data memory and can be used as a chip select signal. the write ( wr ) signal indicates a write operation and can be used as a write strobe. the read ( rd ) signal indicates a read operation and can be used as a read strobe or output enable signal. the adsp-21xx processors support memory-mapped i/o, with the peripherals memory-mapped into the data memory address space and accessed by the processor in the same manner as data memory. data memory map adsp-2101/adsp-2103/adsp-2111 for the adsp-2101, adsp-2103, and adsp-2111, on-chip data memory ram resides in the 1k words beginning at address 0x3800, as shown in figure 10. data memory locations from 0x3c00 to the end of data memory at 0x3fff are reserved. control and status registers for the system, timer, wait-state configuration, and serial port operations are located in this region of memory. adsp-2105/adsp-2115 for the adsp-2105 and adsp-2115, on-chip data memory ram resides in the 512 words beginning at address 0x3800, also shown in figure 10. data memory locations from 0x3a00 to the end of data memory at 0x3fff are reserved. control and status registers for the system, timer, wait-state configuration, and serial port operations are located in this region of memory. figure 10. data memory map (all processors) 0x3a00 0x0400 0x0000 1k external dwait0 1k external dwait1 10k external dwait2 1k external dwait3 0x0800 0x3000 512 for adsp-2105 adsp-2115 adsp-216x external ram internal ram 0x3c00 0x3fff 1k for adsp-2101 adsp-2103 adsp-2111 memory-mapped control registers & reserved 1k external dwait4 0x3400 0x3800
adsp-21xx rev. b C13C if the adsp-21xx is performing an external memory access when the external device asserts the br signal, it will not three- state the memory interfaces or assert the bg signal until the cycle after the access completes (up to eight cycles later depend- ing on the number of wait states). the instruction does not need to be completed when the bus is granted; the adsp-21xx will grant the bus in between two memory accesses if an instruction requires more than one external memory access. when the br signal is released, the processor releases the bg signal, re-enables the output drivers and continues program execution from the point where it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. if this feature is not used, the br input should be tied high (to v dd ). low power idle instruction the idle instruction places the adsp-21xx processor in low power state in which it waits for an interrupt. when an interrupt occurs, it is serviced and execution continues with instruction following idle. typically this next instruction will be a jump back to the idle instruction. this implements a low-power standby loop. the idle n instruction is a special version of idle that slows the processors internal clock signal to further reduce power consumption. the reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor, n , given in the idle instruction. the syntax of the instruction is: idle n ; where n = 16, 32, 64, or 128. the instruction leaves the chip in an idle state, operating at the slower rate. while it is in this state, the processors other internal clock signals, such as sclk, clkout, and the timer clock, are reduced by the same ratio. upon receipt of an enabled interrupt, the processor will stay in the idle state for up to a maximum of n clkin cycles, where n is the divisor specified in the instruction, before resuming normal operation. when the idle n instruction is used, it slows the processors internal clock and thus its response time to incoming interruptsC the 1-cycle response time of the standard idle state is in- creased by n , the clock divisor. when an enabled interrupt is received, the adsp-21xx will remain in the idle state for up to a maximum of n clkin cycles (where n = 16, 32, 64, or 128) before resuming normal operation. when the idle n instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n clkin cycles). adsp-216x prototyping you can prototype your adsp-216x system with either the adsp-2101 or adsp-2103 ram-based processors. when code is fully developed and debugged, it can be submitted to analog devices for conversion into a adsp-216x rom product. the adsp-2101 ez-ice emulator can be used for develop- ment of adsp-216x systems. for the 3.3 v adsp-2162 and adsp-2164, a voltage converter interface board provides 3.3 v emulation. additional overlay memory is used for emulation of adsp- 2161/62 systems. it should be noted that due to the use of off- chip overlay memory to emulate the adsp-2161/62, a perfor- mance loss may be experienced when both executing instruc- tions and fetching program memory data from the off-chip overlay memory in the same cycle. this can be overcome by locating program memory data in on-chip memory. ordering procedure for adsp-216x rom processors to place an order for a custom rom-coded adsp-2161, adsp-2162, adsp-2163, or adsp-2164 processor, you must: 1. complete the following forms contained in the adsp rom ordering package , available from your analog devices sales representative: adsp-216x rom specification form rom release agreement rom nre agreement & minimum quantity order (mqo) acceptance agreement for pre-production rom products 2. return the forms to analog devices along with two copies of the memory image file (.exe file) of your rom code. the files must be supplied on two 3.5" or 5.25" floppy disks for the ibm pc (dos 2.01 or higher). 3. place a purchase order with analog devices for non-recurring engineering changes (nre) associated with rom product development. after this information is received, it is entered into analog devices rom manager system which assigns a custom rom model number to the product. this model number will be branded on all prototype and production units manufactured to these specifications. to minimize the risk of code being altered during this process, analog devices verifies that the .exe files on both floppy disks are identical, and recalculates the checksums for the .exe file entered into the rom manager system. the checksum data, in the form of a rom memory map, a hard copy of the .exe file, and a rom data verification form are returned to you for inspection.
adsp-21xx C14C rev. b a signed rom verification form and a purchase order for production units are required prior to any product being manufactured. prototype units may be applied toward the minimum order quantity. upon completion of prototype manufacture, analog devices will ship prototype units and a delivery schedule update for production units. an invoice against your purchase order for the nre charges is issued at this time. there is a charge for each rom mask generated and a mini- mum order quantity. consult your sales representative for details. a separate order must be placed for parts of a specific package type, temperature range, and speed grade. package & speed lot # & revision code date code ? ? ? functional differences for older revision devices older revisions of the adsp-21xx processors have slight differences in functionality. the two differences are as follows: ? bus grant ( bg ) is asserted in the same cycle that bus request ( br ) is recognized (i.e. when setup and hold time requirements are met for the br input). bus request input is a synchronous input rather than asynchronous. (in newer revision devices, bg is asserted in the cycle after br is recognized.) ? only the standard idle instruction is available, not the clock-reducing idle n instruction. to determine the revision of a particular adsp-21xx device, inspect the marking on the device. for example, an adsp-2101 of revision 6.0 will have the following marking: the revision codes for the older versions of each adsp-21xx device are as follows: processor old functionality new functionality adsp-2101 revision code 5.0 revision code 3 6.0 adsp-2105 no revision code revision code 3 1.0 adsp-2115 revision code < 1.0 revision code 3 1.0 adsp-2111 revisioncode < 2.0 revision code 3 2.0 adsp-2103 revision code 5.0 revision code 3 6.0 a adsp-2101 ks-66 ee/a12345-6.0 d 9234
adsp-21xx rev. b C15C instruction set the adsp-21xx assembly language uses an algebraic syntax for ease of coding and readability. the sources and destinations of computations and data movements are written explicitly in each assembly statement, eliminating cryptic assembler mnemonics. every instruction assembles into a single 24-bit word and executes in a single cycle. the instructions encompass a wide variety of instruction types along with a high degree of operational parallelism. there are five basic categories of instructions: data move instructions, computational instruc- tions, multifunction instructions, program flow control instruc- tions and miscellaneous instructions. multifunction instructions perform one or two data moves and a computation. the instruction set is summarized below. the adsp-2100 family users manual contains a complete reference to the instruction set. alu instructions [if cond] ar|af = xop + yop [+ c] ; add/add with carry = xop C yop [+ cC 1] ; subtract x C y/subtract x C y with borrow = yop C xop [+ cC 1] ; subtract y C x/subtract y C x with borrow = xop and yop ; and = xop or yop ; or = xop xor yop ; xor = pass xop ; pass, clear = C xop ; negate = not xop ; not = abs xop ; absolute value = yop + 1 ; increment = yop C 1 ; decrement = divs yop, xop ; divide = divq xop ; mac instructions [if cond] mr|mf = xop * yop ; multiply = mr + xop * yop ; multiply/accumulate = mr C xop * yop ; multiply/subtract = mr ; transfer mr =0 ; clear if mv sat mr ; conditional mr saturation shifter instructions [if cond] sr = [sr or] ashift xop ; arithmetic shift [if cond] sr = [sr or] lshift xop ; logical shift sr = [sr or] ashift xop by ; arithmetic shift immediate sr = [sr or] lshift xop by ; logical shift immediate [if cond] se = exp xop ; derive exponent [if cond] sb = expadj xop ; block exponent adjust [if cond] sr = [sr or] norm xop ; normalize data move instructions reg = reg ; register-to-register move reg = ; load register immediate reg = dm () ; data memory read (direct address) dreg = dm (ix , my) ; data memory read (indirect address) dreg = pm (ix , my) ; program memory read (indirect address) dm () = reg ; data memory write (direct address) dm (ix , my) = dreg ; data memory write (indirect address) pm (ix , my) = dreg ; program memory write (indirect address) multifunction instructions || , dreg = dreg ; computation with register-to-register move || , dreg = dm (ix , my) ; computation with memory read || , dreg = pm (ix , my) ; computation with memory read dm (ix , my) = dreg , || ; computation with memory write pm (ix , my) = dreg , || ; computation with memory write dreg = dm (ix , my) , dreg = pm (ix , my) ; data & program memory read | , dreg = dm (ix , my) , dreg = pm (ix , my) ; alu/mac with data & program memory read
adsp-21xx C16C rev. b program flow instructions do [until term] ; do until loop [if cond] jump (ix) ; jump [if cond] jump ; [if cond] call (ix) ; call subroutine [if cond] call ; if [not ] flag_in jump ; jump/call on flag in pin if [not ] flag_in call ; [if cond] set|reset|toggle flag_out [, ...] ; modify flag out pin [if cond] rts ; return from subroutine [if cond] rti ; return from interrupt service routine idle [(n)] ; idle miscellaneous instructions nop ; no operation modify (ix , my); modify address register [push sts] [, pop cntr] [, pop pc] [, pop loop] ; stack control ena|dis sec_reg [, ...] ; mode control bit_rev av_latch ar_sat m_mode timer g_mode assembly code example the following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared algorithm. notice that the computations in the instructions are written like algebraic equations. mf=mx0 * my1 ( rnd), mx0=dm(i2,m1); {mf=error * beta} mr=mx0 * mf ( rnd), ay0=pm(i6,m5); do adapt until ce; ar=mr1+ay0, mx0=dm(i2,m1), ay0=pm(i6,m7); adapt: pm(i6,m6)= a r, mr=mx0 * mf ( rnd); modify(i2,m3); {point to oldest data} modify(i6,m7); {point to start of data} notation conventions ix index registers for indirect addressing my modify registers for indirect addressing immediate data value immediate address value exponent (shift value) in shift immediate instructions (8-bit signed number) any alu instruction (except divide) any multiply-accumulate instruction any shift instruction (except shift immediate) cond condition code for conditional instruction term termination code for do until loop dreg data register (of alu, mac, or shifter) reg any register (including dregs) ; a semicolon terminates the instruction , commas separate multiple operations of a single instruction [ ] optional part of instruction [, ...] optional, multiple operations of an instruction option1 | option2 list of options; choose one.
rev. b C17C adsp-2101/2105/2115/2161/2163Cspecifications caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-21xx processors feature proprietary esd protection circuitry to dissipate high energy electrostatic discharges (human body model), permanent damage may occur to devices subjected to such discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before the devices are removed. per method 3015 of mil-std-883, the adsp-21xx processors have been classified as class 1 devices. recommended operating conditions k grade b grade t grade parameter min max min max min max unit v dd supply voltage 4.50 5.50 4.50 5.50 4.50 5.50 v t amb ambient operating temperature 0 +70 C40 +85 C55 +125 c see environmental conditions for information on thermal specifications. electrical characteristics parameter test conditions min max unit v ih hi-level input voltage 3, 5 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 2, 3, 7 @ v dd = min, i oh = C0.5 ma 2.4 v @ v dd = min, i oh = C100 m a 8 v dd C 0.3 v v ol lo-level output voltage 2, 3, 7 @ v dd = min, i ol = 2 ma 0.4 v i ih hi-level input current 1 @ v dd = max, v in = v dd max 10 m a i il lo-level input current 1 @ v dd = max, v in = 0 v 10 m a i ozh tristate leakage current 4 @ v dd = max, v in = v dd max 6 10 m a i ozl tristate leakage current 4 @ v dd = max, v in = 0 v 6 10 m a c i input pin capacitance 1, 8, 9 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 4, 8, 9, 10 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 input-only pins: clkin, reset , irq2 , br , mmap, dr1, dr0 (not on adsp-2105). 2 output pins: bg , pms , dms , bms , rd , wr , a0Ca13, clkout, dt1, dt0 (not on adsp-2105). 3 bidirectional pins: d0Cd23, sclk1, rfs1, tfs1, sclk0 (not on adsp-2105), rfs0 (not on adsp-2105), tfs0 (not on adsp-2105). 4 tristatable pins: a0Ca13, d0Cd23, pms , dms , bms , rd , wr , dt1, sclk1, rsf1, tfs1, dt0 (not on adsp-2105), sclk0 (not on adsp-2105), rfs0 (not on adsp-2105), tfs0 (not on adsp-2105). 5 input-only pins: reset , irq2 , br , mmap, dr1, dr0 (not on adsp-2105). 6 0 v on br , clkin active (to force tristate condition). 7 although specified for ttl outputs, all adsp-21xx outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 8 guaranteed but not tested. 9 applies to pga, plcc, pqfp package types. 10 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . C55oc to +125oc storage temperature range . . . . . . . . . . . . . C65oc to +150oc lead temperature (10 sec) pga . . . . . . . . . . . . . . . . . +300oc lead temperature (5 sec) plcc, pqfp, tqfp . . . . +280oc *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device adsp-21xx
adsp-21xx C18C rev. b specifications (adsp-2101/2105/2115/2161/2163) supply current & power (adsp-2101/2105/2115/2161/2163) parameter test conditions min max unit i dd supply current (dynamic) 1 @ v dd = max, t ck = 40 ns 2 38 ma @ v dd = max, t ck = 50 ns 2 31 ma @ v dd = max, t ck = 72.3 ns 2 24 ma i dd supply current (idle) 1, 3 @ v dd = max, t ck = 40 ns 4 12 ma @ v dd = max, t ck = 50 ns 11 ma @ v dd = max, t ck = 72.3 ns 10 ma notes 1 current reflects device operating with no output loads. 2 v in = 0.4 v and 2.4 v. 3 idle refers to adsp-21xx state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 4 adsp-2105 is not available in a 25 mhz speed grade. for typical supply current (internal power dissipation) figures, see figure 11. figure 11. adsp-2101 power (typical) vs. frequency valid for all temperature grades. 1 power reflects device operating with no output loads. 2 idle refers to adsp-21xx operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 3 maximum power dissipation at v dd = 5.5v during execution of idle n instruction. power ?mw 30.00 20.00 13.83 10.00 25.00 30 45 35 40 50 60 55 65 idle 128 idd idle idle 16 51mw 41mw 40mw 64mw 43mw 42mw frequency ?mhz idd idle n modes 3 power ?mw 30.00 20.00 13.83 10.00 25.00 80 60 140 100 120 160 200 180 220 129mw 100mw 74mw 205mw 157mw 118mw frequency ?mhz idd dynamic 1 v dd = 5.5v v dd = 5.0v v dd = 4.5v power ?mw 30.00 20.00 13.83 10.00 25.00 0 30 10 20 40 60 50 70 51mw 38mw 28mw 64mw 49mw 35mw frequency ?mhz idd idle 1,2 v dd = 5.5v v dd = 5.0v v dd = 4.5v
adsp-21xx rev. b C19C power dissipation example to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an adsp-2101 application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 5.0 v and t ck = 50 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation (from figure 11). ( c v dd 2 f ) is calculated for each output: # of output pins c v dd 2 f address, dms 8 10 pf 5 2 v 20 mhz = 40.0 mw data, wr 9 10 pf 5 2 v 10 mhz = 22.5 mw rd 1 10 pf 5 2 v 10 mhz = 2.5 mw clkout 1 10 pf 5 2 v 20 mhz = 5.0 mw 70.0 mw total power dissipation for this example = p int + 70.0 mw. environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package q ja q jc q ca pga 18 c/w 9 c/w 9 c/w plcc 27 c/w 16 c/w 11 c/w pqfp 60 c/w 18 c/w 42 c/w tqfp 60 c/w 18 c/w 42 c/w specifications (adsp-2101/2105/2115/2161/2163) capacitive loading figures 12 and 13 show capacitive loading characteristics for the adsp-2101, adsp-2105, adsp-2115, and adsp-2161/2163. c l ?pf 25 150 125 100 75 50 rise time (0.8v - 2.0v) ?ns v dd = 4.5v 8 7 6 5 4 3 2 1 0 175 0 figure 12. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) figure 13. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) c l ?pf 25 100 125 50 75 150 valid output delay or hold ?ns v dd = 4.5v 175 0 5 4 3 2 1 0 ? ? ?
adsp-21xx C20C rev. b test conditions figure 14 shows voltage reference levels for ac measurements. figure 14. voltage reference levels for ac measurements (except output enable/disable) output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in figure 15. the time t measured is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitative load, c l , and the current load, i l , on the output pin. it can be approximated by the following equation: t decay = c l 0.5 v i l from which t dis = t measured C t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in figure 15. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. specifications (adsp-2101/2105/2115/2161/2163) 3.0v 1.5v 0.0v 2.0v 1.5v 0.8v input output figure 15. output enable/disable to output pin 50pf +1.5v i oh i ol figure 16. equivalent device loading for ac measurements (except output enable/disable) 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) ?0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured)
adsp-2111Cspecifications recommended operating conditions k grade b grade t grade parameter min max min max min max unit v dd supply voltage 4.50 5.50 4.50 5.50 4.50 5.50 v t amb ambient operating temperature 0 +70 C40 +85 C55 +125 c see environmental conditions for information on thermal specifications. electrical characteristics parameter test conditions min max unit v ih hi-level input voltage 3, 5 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 2, 3, 7 @ v dd = min, i oh = C0.5 ma 2.4 v @ v dd = min, i oh = C100 m a 8 v dd C 0.3 v v ol lo-level output voltage 2, 3, 7 @ v dd = min, i ol = 2 ma 0.4 v i ih hi-level input current 1 @ v dd = max, v in = v dd max 10 m a i il lo-level input current 1 @ v dd = max, v in = 0v 10 m a i ozh tristate leakage curren 4 @ v dd = max, v in = v dd max 6 10 m a i ozl tristate leakage current 4 @ v dd = max, v in = 0v 6 10 m a c i input pin capacitance 1, 8, 9 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 4, 8, 9, 10 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 input-only pins: clkin, reset , i rq2 , br , mmap, dr1, dr0, hsel , hsize, bmode, hmd0, hmd1, hrd /hrw, hwr / hds , ha2/ale, ha1-0. 2 output pins: bg , pms , dms , bms , rd , wr , a0Ca13, clkout, dt1, dt0, hack , fl2-0. 3 bidirectional pins: d0Cd23, sclk1, rfs1, tfs1, sclk0, rfs0, tfs0, hd0Chd15/had0Chad15. 4 tristatable pins: a0Ca13, d0Cd23, pms , dms , bms , rd , wr , dt1, sclk1, rsf1, tfs1, dt0, sclk0, rfs0, tfs0, hd0Chd15/had0Chad15. 5 input-only pins: reset , irq2 , br , mmap, dr1, dr0, hsel , hsize, bmode, hmd0, hmd1, hrd /hrw, hwr / hds , ha2/ale, ha1-0. 6 0 v on br , clkin active (to force tristate condition). 7 although specified for ttl outputs, all adsp-2111 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 8 guaranteed but not tested. 9 applies to adsp-2111 pga and pqfp packages. 10 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . C55oc to +125oc storage temperature range . . . . . . . . . . . . . C65oc to +150oc lead temperature (10 sec) pga . . . . . . . . . . . . . . . . . +300oc lead temperature (5 sec) pqfp . . . . . . . . . . . . . . . . . +280oc *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. adsp-21xx rev. b C21C
adsp-21xx C22C rev. b supply current & power (adsp-2111) parameter test conditions min max unit i dd supply current (dynamic) 1 @ v dd = max, t ck = 50 ns 2 60 ma @ v dd = max, t ck = 60 ns 2 52 ma @ v dd = max, t ck = 76.9 ns 2 46 ma i dd supply current (idle) 1, 3 @ v dd = max, t ck = 50 ns 18 ma @ v dd = max, t ck = 60 ns 16 ma @ v dd = max, t ck = 76.9 ns 14 ma notes 1 current reflects device operating with no output loads. 2 v in = 0.4 v and 2.4 v. 3 idle refers to adsp-21xx state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. for typical supply current (internal power dissipation) figures, see figure 17. specifications (adsp-2111) figure 17. adsp-2111 power (typical) vs. frequency power (p i dle ) ?mw power, idle 1,2 50 30 40 80 60 70 90 100 20 18 17 16 15 14 19 100mw 70mw 50mw 1 / t ck ?mhz 40mw 55mw 80mw power, idle n modes 3 40 30 35 55 45 50 60 65 70 idle; 32mw 34mw idle 16; idle 128; 70mw 55mw 20 18 17 16 15 14 19 36mw 38mw power (p idle n ) ?mw 1 / t ck ?mhz valid for all temperature grades. 1 power reflects device operating with no output loads. 2 idle refers to adsp-21xx operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 3 maximum power dissipation at v dd = 5.0v during execution of idle n instruction. power (p int ) ?mw 20 18 17 16 15 14 19 1 / t ck ?mhz 330mw 260mw 200mw 250mw 200mw 155mw power, internal 1 190 150 170 250 210 230 270 310 290 330 v dd = 5.5v v dd = 5.0v v dd = 4.5v v dd = 5.5v v dd = 5.0v v dd = 4.5v v dd = 5.0v
adsp-21xx rev. b C23C power dissipation example to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an adsp-2111 application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 5.0 v and t ck = 50 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation (from figure 17). ( c v dd 2 f ) is calculated for each output: # of output pins c v dd 2 f address, dms 8 10 pf 5 2 v 20 mhz = 40.0 mw data, wr 9 10 pf 5 2 v 10 mhz = 22.5 mw rd 1 10 pf 5 2 v 10 mhz = 2.5 mw clkout 1 10 pf 5 2 v 20 mhz = 5.0 mw 70.0 mw total power dissipation for this example = p int + 70.0 mw. environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package q ja q jc q ca pga 35 c/w 18 c/w 17 c/w pqfp 42 c/w 18 c/w 23 c/w specifications (adsp-2111) capacitive loading figures 18 and 19 show capacitive loading characteristics for the adsp-2111. c l ?pf 25 150 125 100 75 50 rise time (0.8v - 2.0v) ?ns 14 2 6 4 8 10 12 v dd = 4.5v figure 18. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) c l ?pf 25 100 125 50 75 150 valid output delay or hold ?ns +10 ? ? ? +4 +2 +6 +8 +12 nominal v dd = 4.5v figure 19. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature)
adsp-21xx C24C rev. b specifications (adsp-2111) the decay time, t decay , is dependent on the capacitative load, c l , and the current load, i l , on the output pin. it can be approximated by the following equation: t decay = c l 0.5 v i l from which t dis = t measured C t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in figure 21. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. test conditions figure 20 shows voltage reference levels for ac measurements. figure 20. voltage reference levels for ac measurements (except output enable/disable) output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in figure 21. the time t measured is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. 3.0v 1.5v 0.0v 2.0v 1.5v 0.8v input output figure 22. equivalent device loading for ac measurements (except output enable/disable) 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) ?0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 21. output enable/disable to output pin 50pf +1.5v i oh i ol
recommended operating conditions k grade b grade parameter min max min max unit v dd supply voltage 3.00 3.60 3.00 3.60 v t amb ambient operating temperature 0 +70 C40 +85 c see environmental conditions for information on thermal specifications. electrical characteristics parameter test conditions min max unit v ih hi-level input voltage 1, 3 @ v dd = max 2.0 v v il lo-level input voltage 1, 3 @ v dd = min 0.4 v v oh hi-level output voltage 2, 3, 6 @ v dd = min, i oh = C0.5 ma 6 2.4 v v ol lo-level output voltage 2, 3, 6 @ v dd = min, i ol = 2 ma 6 0.4 v i ih hi-level input current 1 @ v dd = max, v in = v dd max 10 m a i il lo-level input current 1 @ v dd = max, v in = 0 v 10 m a i ozh tristate leakage current 4 @ v dd = max, v in = v dd max 5 10 m a i ozl tristate leakage current 4 @ v dd = max, v in = 0 v 5 10 m a c i input pin capacitance 1, 7, 8 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 4, 7, 8, 9 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 input-only pins: clkin, reset, irq2, br, mmap, dr1, dr0. 2 output pins: bg, pms, dms, bms, rd, wr, a0Ca13, clkout, dt1, dt0. 3 bidirectional pins: d0Cd23, sclk1, rfs1, tfs1, sclk0, rfs0, tfs0. 4 tristatable pins: a0Ca13, d0Cd23, pms, dms, bms, rd, wr, dt1, sclk1, rsf1, tfs1, dt0, sclk0, rfs0, tfs0. 5 0 v on br, clkin active (to force tristate condition). 6 all adsp-2103, adsp-2162, and adsp-2164 outputs are cmos and will drive to v dd and gnd with no dc loads. 7 guaranteed but not tested. 8 applies to plcc and pqfp package types. 9 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. adsp-2103/2162/2164Cspecifications absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +4.5 v input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . . C40oc to +85oc storage temperature range . . . . . . . . . . . . . C65oc to +150oc lead temperature (5 sec) plcc, pqfp . . . . . . . . . . . +280oc *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. adsp-21xx C25C rev. b
adsp-21xx C26C rev. b specifications (adsp-2103/2162/2164) supply current & power (adsp-2103/2162/2164) parameter test conditions min max unit i dd supply current (dynamic) 1 @ v dd = max, t ck = 72.3 ns 2 14 ma i dd supply current (idle) 1, 3 @ v dd = max, t ck = 72.3 ns 4 ma notes 1 current reflects device operating with no output loads. 2 v in = 0.4 v and 2.4 v. 3 idle refers to adsp-21xx state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. for typical supply current (internal power dissipation) figures, see figure 23. valid for all temperature grades. 1 power reflects device operating with no output loads. 2 idle refers to adsp-21xx operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 3 maximum power dissipation at v dd = 3.6v during execution of idle n instruction. 4 0 2 10 6 8 12 14 15.00 13.83 10.00 7.00 5.00 power ?mw idd idle frequency ?mhz 9mw 6mw 5mw 13mw 10mw 8mw 1 15 5 10 30 20 25 35 50 power ?mw idle dynamic 1,2 frequency ?mhz 48mw 37mw 29mw 15mw 15.00 13.83 10.00 7.00 5.00 45 40 0 24mw 19mw 4 0 2 10 6 8 12 14 15.00 13.83 10.00 7.00 5.00 power ?mw frequency ?mhz idle 128 idle 16 idd idle 9mw 5mw 4mw 13mw 7mw 6mw idd idle n modes 3 v dd = 3.6v v dd = 3.30v v dd = 3.0v v dd = 3.6v v dd = 3.30v v dd = 3.0v figure 23. adsp-2103 power (typical) vs. frequency
adsp-21xx rev. b C27C power dissipation example to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an adsp-2103 application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 3.3 v and t ck = 100 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation (from figure 23). ( c v dd 2 f ) is calculated for each output: # of output pins c v dd 2 f address, dms 8 10 pf 3.3 2 v 10 mhz = 8.71 mw data, wr 9 10 pf 3.3 2 v 5 mhz = 4.90 mw rd 1 10 pf 3.3 2 v 5 mhz = 0.55 mw clkout 1 10 pf 3.3 2 v 10 mhz = 1.09 mw 15.25 mw total power dissipation for this example = p int + 15.25 mw. environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package q ja q jc q ca pga 27 c/w 16 c/w 11 c/w pqfp 60 c/w 18 c/w 42 c/w specifications (adsp-2103/2162/2164) figure 25. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) figure 24. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) capacitive loading figures 24 and 25 show capacitive loading characteristics for the adsp-2103, adsp-2162, and adsp-2164. 25 150 125 100 75 c l ?pf 50 rise time (0.8v-2.0v) ?ns 30 10 5 15 20 25 v dd = 3.0v valid output delay or hold ?ns ? +4 +2 +6 nominal 25 150 125 100 75 c l ?pf 50 +8 v dd = 3.0v
adsp-21xx C28C rev. b the decay time, t decay , is dependent on the capacitative load, c l , and the current load, i l , on the output pin. it can be approximated by the following equation: t decay = c l 0.5 v i l from which t dis = t measured C t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in figure 27. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. specifications (adsp-2103/2162/2164) test conditions figure 26 shows voltage reference levels for ac measurements. figure 26. voltage reference levels for ac measurements (except output enable/disable) output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in figure 27. the time t measured is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. input output v dd 2 v dd 2 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) ?0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) to output pin 50pf i oh i ol v dd 2 figure 27. output enable/disable figure 28. equivalent device loading for ac measurements (except output enable/disable)
adsp-21xx rev. b C29C general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use timing parameters (adsp-2101/2105/2111/2115/2161/2163) switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. memory requirements the table below shows common memory device specifications and the corresponding adsp-21xx timing parameters, for your convenience. memory adsp-21xx timing device timing parameter specification parameter definition address setup to write start t asw a0Ca13, dms, pms setup before wr low address setup to write end t aw a0Ca13, dms, pms setup before wr deasserted address hold time t wra a0Ca13, dms, pms hold after wr deasserted data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access time t aa a0Ca13, dms, pms, bms to data valid
adsp-21xx C30C rev. b timing parameters (adsp-2101/2105/2111/2115/2161/2163) clock signals & reset frequency 13 mhz 13.824 mhz 16.67 mhz 20 mhz 25 mhz dependency parameter min max min max min max min max min max min max unit timing requirement: t ck clkin period 76.9 150 72.3 150 60 150 50 150 40 150 ns t ckl clkin width low 20 20 20 20 15 20 ns t ckh clkin width high 20 20 20 20 15 20 ns t rsp reset width low 384.5 361.5 300 250 200 5t ck 1 ns switching characteristic: t cpl clkout width low 28.5 26.2 20 15 10 0.5t ck C 10 ns t cph clkout width high 28.5 26.2 20 15 10 0.5t ck C 10 ns t ckoh clkin high to clkout 0 20 0 20 0 20 0 20 0 15 ns high notes 1 applies after powerup sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles, assuming stable clkin (not including crystal oscillator startup time). figure 29. clock signals clkin clkout t ckh t ck t ckl t ckoh t cph t cpl
adsp-21xx rev. b C31C timing parameters (adsp-2101/2105/2111/2115/2161/2163) frequency 13 mhz 13.824 mhz 16.67 mhz 20 mhz 25 mhz dependency parameter min max min max min max min max min max min max unit timing requirement: t ifs irqx 1 or fi setup before 34.2 33.1 30 27.5 25 0.25t ck + 15 4 ns clkout low 2, 3 t ifs irqx 1 or fi setup before 37.2 36.1 33 30.5 28 0.25t ck + 18 4 ns clkout low (adsp-2111) 2, 3 t ifh irqx 1 or fi hold after clkout 19.2 18.1 15 12.5 10 0.25t ck ns high 2, 3 switching characteristic: t foh fo hold after clkout high 5 00 0000 ns t fod fo delay from clkout high 15 15 15 15 12 ns notes 1 irqx= irq0, irq1, and irq2. 2 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the following cycle. (refer to the interrupt controller section in chapter 3, program control, of the adsp-2100 family users manual for further information on interrupt servicing.) 3 edge-sensitive interrupts require pulse widths greater than 10 ns. level-sensitive interrupts must be held low until serviced. 4 t ifs (min) = 0.25t ck + 20 ns for adsp-2101tg-50, adsp-2101tg/883b-50, adsp-2111tg-52, and adsp-2111tg/883b-52 ( extended temperature range devices). 5 t foh (min) = C5 ns for adsp-2111tg-52 and adsp-2111tg/883b-52 (extended temperature range devices). interrupts & flags figure 30. interrupts & flags clkout flag output(s) t fod irq x fi t foh t ifh t ifs
adsp-21xx C32C rev. b frequency 13 mhz 13.824 mhz 16.67 mhz 20 mhz 25 mhz dependency parameter min max min max min max min max min max min max unit timing requirement: t bh br hold after clkout high 1 24.2 23.1 20 17.5 15 0.25t ck + 5 ns t bs br setup before clkout low 1 39.2 38.1 35 32.5 30 0.25t ck + 20 ns switching characteristic: t sd clkout high to dms, 39.2 38.1 35 32.5 30 0.25t ck + 20 ns pms, bms, rd, wr disable t sdb dms, pms, bms, rd, wr00 0 000 ns disable to bg low t se bg high to dms, pms, 0 0 0 0 0 0 ns bms, rd, wr enable t sec dms, pms, bms, rd, wr 9.2 8.1 5 2.5 1.5 2 0.25t ck C 10 2 ns enable to clkout high notes 1 if br meets the t bs and t bh setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. br requires a pulse width greater than 10 ns. 2 for 25 mhz only the minimum frequency dependency formula for t sec = (0.25t ck C 8.5). section 10.2.4, bus request/grant, on page 212 of the adsp-2100 family users manual (1st edition, 1993) states that when br is recognized, the processor responds immediately by asserting bg during the same cycle. this is incorrect for the current versions of all adsp-21xx processors: bg is asserted in the cycle after br is recognized. no external synchronization circuit is needed when br is generated as an asynchronous signal. timing parameters (adsp-2101/2105/2111/2115/2161/2163) bus request/grant clkout pms , dms bms , rd wr t bs br bg clkout t sd t sdb t se t sec t bh figure 31. bus request/grant
adsp-21xx rev. b C33C frequency dependency (clkin 25 mhz) parameter min max unit timing requirement: t rdd rd low to data valid 0.5t ck C 13 + w ns t aa a0Ca13, pms, dms, bms to data valid 0.75t ck C 18 + w ns t rdh data hold from rd high 0 switching characteristic: t rp rd pulse width 0.5t ck C 8 + w ns t crd clkout high to rd low 0.25t ck C 5 0.25t ck + 10 ns t asr a0Ca13, pms, dms, bms setup before rd low 0.25t ck C 10 1 ns t rda a0Ca13, pms, dms, bms hold after rd deasserted 0.25t ck C 9 ns t rwr rd high to rd or wr low 0.5t ck C 5 ns notes 1 for 25 mhz only minimum frequency dependency formula for t asr = (0.25t ck C 8.5). w = wait states t ck. timing parameters (adsp-2101/2105/2111/2115/2161/2163) memory read figure 32. memory read clkout a0 ?a13 d t rda rd wr dms, pms bms t rwr t rp t asr t crd t rdd t aa t rdh 13 mhz 13.824 mhz 16.67 mhz 20 mhz 25 mhz parameter min max min max min max min max min max unit timing requirement: t rdd rd low to data valid 23.5 23.2 17 12 7 ns t aa a0Ca13, pms, dms, bms to data valid 37.7 36.2 27 19.5 12 ns t rdh data hold from rd high 0 0 0 0 0 ns switching characteristic: t rp rd pulse width 33.5 28.2 22 17 12 ns t crd clkout high to rd low 14.2 29.2 13.1 28.1 10 25 7.5 22.5 5 20 ns t asr a0Ca13, pms, dms, bms setup before 9.2 8.1 5 2.5 1.5 1 ns rd low t rda a0Ca13, pms, dms, bms hold after rd 10.2 9.1 6 3.5 1 ns deasserted t rwr rd high to rd or wr low 33.5 31.2 25 20 15 ns
adsp-21xx C34C rev. b timing parameters (adsp-2101/2105/2111/2115/2161/2163) memory write 13 mhz 13.824 mhz 16.67 mhz 20 mhz 25 mhz parameter min max min max min max min max min max unit switching characteristic: t dw data setup before wr high 25.5 23.2 17 12 7 ns t dh data hold after wr high 9.2 8.1 5 2.5 0 ns t wp wr pulse width 30.5 28.2 22 17 12 ns t wde wr low to data enabled 0 0 0 0 0 ns t asw a0Ca13, dms, pms setup before 9.2 8.1 5 2.5 1.5 1 ns wr low t ddr data disable before wr or rd low 9.2 8.1 5 2.5 1.5 1 ns t cwr clkout high to wr low 14.2 29.2 13.1 28.1 10 25 7.5 22.5 5 20 ns t aw a0Ca13, dms, pms, setup before wr 35.7 32.2 23 15.5 8 ns deasserted t wra a0Ca13, dms, pms hold after wr 10.2 9.1 6 3.5 1 ns deasserted t wwr wr high to rd or wr low 33.5 31.2 25 20 15 ns figure 33. memory write clkout a0 ?a13 d t wr a wr dms, pms t wwr t wp t as w t aw t cwr rd t dh t dd r t wde t dw frequency dependency (clkin 25 mhz) parameter min max unit switching characteristic: t dw data setup before wr high 0.5t ck C 13 + w ns t dh data hold after wr high 0.25t ck C 10 ns t wp wr pulse width 0.5t ck C 8 + w ns t wde wr low to data enabled 0 t asw a0Ca13, dms, pms setup before wr low 0.25t ck C 10 1 ns t ddr data disable before wr or rd low 0.25t ck C 10 1 ns t cwr clkout high to wr low 0.25t ck C 5 0.25t ck + 10 ns t aw a0Ca13, dms, pms, setup before wr deasserted 0.75t ck C 22 + w ns t wra a0Ca13, dms, pms hold after wr deasserted 0.25t ck C 9 ns t wwr wr high to rd or wr low 0.5t ck C 5 ns notes 1 for 25 mhz only the minimum frequency dependency formula for t asw and t ddr = (0.25t ck C 8.5). w = wait states t ck .
adsp-21xx rev. b C35C frequency 12.5 mhz 13.0 mhz 13.824 mhz* dependency parameter min max min max min max min max unit timing requirement: t sck sclk period 80 76.9 72.3 ns t scs dr/tfs/rfs setup before sclk low 8 8 8 ns t sch dr/tfs/rfs hold after sclk low 10 10 10 ns t scp sclk in width 30 28 28 ns switching characteristic: t cc clkout high to sclk out 20 35 19.2 34.2 18.1 33.1 0.25t ck 0.25t ck + 15ns t scde sclk high to dt enable 0 0 0 ns t scdv sclk high to dt valid 20 20 20 ns t rh tfs/rfs out hold after sclk high 0 0 0 ns t rd tfs/rfs out delay from sclk high 20 20 20 ns t scdh dt hold after sclk high 0 0 0 ns t tde tfs (alt) to dt enable 0 0 0 ns t tdv tfs (alt) to dt valid 18 18 18 ns t scdd sclk high to dt disable 25 25 25 ns t rdv rfs (multichannel, frame delay zero) 20 20 20 ns to dt valid *maximum serial port operating frequency is 13.824 mhz for all processor speed grades except the 12.5 mhz adsp-2101 and 13.0 mhz adsp-2111. timing parameters (adsp-2101/2105/2111/2115/2161/2163) serial ports clkout sclk tfs rfs dr rfs in tfs in dt ( alternate frame mode ) t cc t cc t sck t scp t scp t scs t sch t rd t rh rfs out tfs out t scdv t scde t scdh t scdd t tde t tdv t rdv ( multichannel mode, frame delay 0 {mfd = 0} ) figure 34. serial ports
adsp-21xx C36C rev. b timing parameters (adsp-2111) host interface port separate data & address (hmd1 = 0 ) read strobe & write strobe (hmd0 = 0) 13.0 mhz 16.67 mhz 20 mhz no frequency parameter min max min max min max dependency unit timing requirement: t hsu ha2-0 setup before start of write or read 1, 2 888 ns t hdsu data setup before end of write 3 888 ns t hwdh data hold after end of write 3 333 ns t hh ha2-0 hold after end of write or read 3, 4 333 ns t hrwp read or write pulse width 5 30 30 30 ns switching characteristic: t hshk hack low after start of write or read 1, 2 020 020 020 ns t hkh hack hold after end of write or read 3, 4 020 020 020 ns t hde data enabled after start of read 2 000 ns t hdd data valid after start of read 2 23 23 23 ns t hrdh data hold after end of read 4 000 ns t hrdd data disabled after end of read 4 10 10 10 ns notes 1 start of write = hwr low and hsel low. 2 start of read = hrd low and hsel low. 3 end of write = hwr high or hsel high. 4 end of read = hrd high or hsel high. 5 read pulse width = hrd low and hsel low, write pulse width = hwr low and hsel low.
adsp-21xx rev. b C37C host write cycle host read cycle figure 35. host interface port (hmd1 = 0, hmd0 = 0) data hd15? hsel hwr hack ha2? address t hsu t hh t hwdh t hrwp t hshk t hkh t hdsu data hd15? hsel h rd hack ha2? address t hsu t hh t hrwp t hrdh t hkh t hshk t hrdd t hde t hdd
adsp-21xx C38C rev. b timing parameters (adsp-2111) host interface port separate data & address (hmd1 = 0) read/write strobe & data strobe (hmd0 = 1) 13.0 mhz 16.67 mhz 20 mhz no frequency parameter min max min max min max dependency unit timing requirement: t hsu ha2-0, hrw setup before start of write or read 1 888 ns t hdsu data setup before end of write 2 888 ns t hwdh data hold after end of write 2 333 ns t hh ha2-0, hrw hold after end of write or read 2 333 ns t hrwp read or write pulse width 3 30 30 30 ns switching characteristic: t hshk hack low after start of write or read 1 020 020 020 ns t hkh hack hold after end of write or read 2 020 020 020 ns t hde data enabled after start of read 1 000 ns t hdd data valid after start of read 1 23 23 23 ns t hrdh data hold after end of read 2 000 ns t hrdd data disabled after end of read 2 10 10 10 ns notes 1 start of write or read = hds low and hsel low. 2 end of write or read = hds high or hsel high. 3 read or write pulse width = hds low and hsel low.
adsp-21xx rev. b C39C figure 36. host interface port (hmd1 = 0, hmd0 =1) host write cycle host read cycle data hd15? hsel hrw hack ha2? address t hsu t hh t hwdh t hrwp t hshk t hkh t hdsu h ds data hd15? hsel h ds hack ha2? address t hsu t hh t hrwp t hrdh t hkh t hshk t hde t hdd hrw t hrdd
adsp-21xx C40C rev. b timing parameters (adsp-2111) host interface port multiplexed data & address (hmd1 = 1) read strobe & write strobe (hmd0 = 0) 13.0 mhz 16.67 mhz 20 mhz no frequency parameter min max min max min max dependency unit timing requirement: t halp ale pulse width 15 15 15 ns t hasu had15-0 address setup before ale low 5 5 5 ns t hah had15-0 address hold after ale low 2 2 2 ns t hals start of write or read after ale low 1, 2 15 15 15 ns t hdsu had15-0 data setup before end of write 3 888 ns t hwdh had15-0 data hold after end of write 3 333 ns t hrwp read or write pulse width 5 30 30 30 ns switching characteristic: t hshk hack low after start of write or read 1, 2 020 020 020 ns t hkh hack hold after end of write or read 3, 4 020 020 020 ns t hde had15-0 data enabled after start of read 2 000 ns t hdd had15-0 data valid after start of read 2 23 23 23 ns t hrdh had15-0 data hold after end of read 4 000 ns t hrdd had15-0 data disabled after end of read 4 10 10 10 ns notes 1 start of write = hwr low and hsel low. 2 start of read = hrd low and hsel low. 3 end of write = hwr high or hsel high. 4 end of read = hrd high or hsel high. 5 read pulse width = hrd low and hsel low, write pulse width = hwr low and hsel low.
adsp-21xx rev. b C41C address t hdsu data hack hwr hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hwdh t hrdh t hrdd t hde address data hack hrd hsel had15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hdd host write cycle figure 37. host interface port (hmd1 = 1, hmd0 = 0) host read cycle
adsp-21xx C42C rev. b timing parameters (adsp-2111) host interface port multiplexed data & address (hmd1 = 1) read/write strobe & data strobe (hmd0 = 1 ) 13.0 mhz 16.67 mhz 20 mhz no frequency parameter min max min max min max dependency unit timing requirement: t halp ale pulse width 15 15 15 ns t hasu had15-0 address setup before ale low 5 5 5 ns t hah had15-0 address hold after ale low 2 2 2 ns t hals start of write or read after ale low 1 15 15 15 ns t hsu hrw setup before start of write or read 1 888 ns t hdsu had15-0 data setup before end of write 2 555 ns t hwdh had15-0 data hold after end of write 2 333 ns t hh hrw hold after end of write or read 2 333 ns t hrwp read or write pulse width 3 30 30 30 ns switching characteristic: t hshk hack low after start of write or read 1 020 020 020 ns t hkh hack hold after end of write or read 2 020 020 020 ns t hde had15-0 data enabled after start of read 1 000 ns t hdd had15-0 data valid after start of read 1 23 23 23 ns t hrdh had15-0 data hold after end of read 2 000 ns t hrdd had15-0 data disabled after end of read 2 10 10 10 ns notes 1 start of write or read = hds low and hsel low. 2 end of write or read = hds high or hsel high. 3 read or write pulse width = hds low and hsel low.
adsp-21xx rev. b C43C host write cycle host read cycle address t hdsu data hack hrw hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hwdh hds t hh t hsu address data hack hrw hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hrdh hds t hh t hsu t hde t hdd t hrdd figure 38. host interface port (hmd1 = 1, hmd0 = 1)
adsp-21xx C44C rev. b timing parameters (adsp-2103/2162/2164) timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. memory requirements the table below shows common memory device specifications and the corresponding adsp-21xx timing parameters, for your convenience. general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. adsp-21xx memory specification timing parameter timing parameter definition address setup to write start t asw a0Ca13, dms, pms setup before wr low address setup to write end t aw a0Ca13, dms, pms setup before wr deasserted address hold time t wra a0Ca13, dms, pms hold after wr deasserted data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access time t aa a0Ca13, dms, pms, bms to data valid
adsp-21xx rev. b C45C frequency 10.24 mhz dependency parameter min max min max unit timing requirement: t ck clkin period 97.6 150 ns t ckl clkin width low 20 ns t ckh clkin width high 20 ns t rsp reset width low 488 5t ck 1 ns switching characteristic: t cpl clkout width low 38.8 0.5t ck C 10 ns t cph clkout width high 38.8 0.5t ck C 10 ns t ckoh clkin high to clkout high 0 20 ns notes 1 applies after powerup sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable clkin (not including crystal oscillator startup time). timing parameters (adsp-2103/2162/2164) clock signals & reset figure 39. clock signals clkin clkout t ckh t ck t ckl t ckoh t cph t cpl
adsp-21xx C46C rev. b timing parameters (adsp-2103/2162/2164) interrupts & flags frequency 10.24 mhz dependency parameter min max min max unit timing requirement: t ifs irqx 1 or fi setup before clkout low 2, 3 44.4 0.25t ck + 20 ns t ifh irqx 1 or fi hold after clkout high 2, 3 24.4 0.25t ck ns switching characteristic: t foh fo hold after clkout high 0 ns t fod fo delay from clkout high 15 ns notes 1 irqx= irq0, irq1, and irq2 . 2 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the following cycle. (refer to the interrupt controller section in chapter 3, program control, of the adsp-2100 family users manual for further information on interrupt servicing.) 3 edge-sensitive interrupts require pulse widths greater than 10 ns. level-sensitive interrupts must be held low until serviced. clkout flag output(s) t fod irq x fi t foh t ifh t ifs figure 40. interrupts & flags
adsp-21xx rev. b C47C timing parameters (adsp-2103/2162/2164) bus request/grant frequency 10.24 mhz dependency parameter min max min max unit timing requirement: t bh br hold after clkout high 1 29.4 0.25t ck + 5 ns t bs br setup before clkout low 1 44.4 0.25t ck + 20 ns switching characteristic: t sd clkout high to dms, pms, bms, rd, wr disable 44.4 0.25t ck + 20 ns t sdb dms, pms, bms, rd, wr disable to bg low 0 ns t se bg high to dms, pms, bms, rd, wr enable 0 ns t sec dms, pms, bms, rd, wr enable to clkout high 14.4 0.25t ck C 10 ns notes 1 if br meets the t bs and t bh setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. br requires a pulse width greater than 10 ns. section 10.2.4, bus request/grant, of the adsp-2100 family users manual (1st edition, ?1993) states that when br is recognized, the processor responds immediately by asserting bg during the same cycle. this is incorrect for the current versions of all adsp-21xx processors: bg is asserted in the cycle after br is recognized. no external synchronization circuit is needed when br is generated as an asynchronous signal. figure 41. bus request/grant clkout pms , dms bms , rd wr t bs br bg clkout t sd t sdb t se t sec t bh
adsp-21xx C48C rev. b timing parameters (adsp-2103/2162/2164) memory read frequency 10.24 mhz dependency parameter min max min max unit timing requirement: t rdd rd low to data valid 33.8 0.5t ck C 15 + w ns t aa a0Ca13, pms, dms, bms to data valid 49.2 0.75t ck C 24 + w ns t rdh data hold from rd high 0 ns switching characteristic: t rp rd pulse width 43.8 0.5t ck C 5 + w ns t crd clkout high to rd low 19.4 34.4 0.25t ck C 5 0.25t ck + 10 ns t asr a0Ca13, pms, dms, bms setup before rd low 12.4 0.25t ck C 12 ns t rda a0Ca13, pms, dms, bms hold after rd deasserted 14.4 0.25t ck C 10 ns t rwr rd high to rd or wr low 38.8 0.5t ck C 10 ns w = wait states t ck. figure 42. memory read clkout a0 ?a13 d t rda rd wr dms, pms bms t rwr t rp t asr t crd t rdd t aa t rdh
adsp-21xx rev. b C49C frequency 10.24 mhz dependency parameter min max min max unit switching characteristic: t dw data setup before wr high 38.8 0.5t ck C 10 + w ns t dh data hold after wr high 14.4 0.25t ck C 10 ns t wp wr pulse width 43.8 0.5t ck C 5 + w ns t wde wr low to data enabled 0 t asw a0Ca13, dms, pms setup before wr low 12.4 0.25t ck C 12 ns t ddr data disable before wr or rd low 14.4 0.25t ck C 10 ns t cwr clkout high to wr low 19.4 34.4 0.25t ck C 5 0.25t ck + 10 ns t aw a0Ca13, dms, pms, setup before wr deasserted 58.2 0.75t ck C 15 + w ns t wra a0Ca13, dms, pms hold after wr deasserted 14.4 0.25t ck C 10 ns t wwr wr high to rd or wr low 38.8 0.5t ck C 10 ns w = wait states t ck. timing parameters (adsp-2103/2162/2164) memory write figure 43. memory write clkout a0 ?a13 d t wr a wr dms, pms t wwr t wp t as w t aw t cwr rd t dh t dd r t wde t dw
adsp-21xx C50C rev. b timing parameters (adsp-2103/2162/2164) serial ports frequency 10.24 mhz dependency parameter min max min max unit timing requirement: t sck sclk period 97.6 t ck ns t scs dr/tfs/rfs setup before sclk low 8 ns t sch dr/tfs/rfs hold after sclk low 10 ns t scp sclk in width 28 ns switching characteristic: t cc clkout high to sclk out 24.4 39.4 0.25t ck 0.25t ck + 15 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 28 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 28 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 18 ns t scdd sclk high to dt disable 30 ns t rdv rfs (multichannel, frame delay zero) 20 ns to dt valid clkout sclk tfs rfs dr rfs in tfs in dt ( alternate frame mode ) t cc t cc t sck t scp t scp t scs t sch t rd t rh rfs out tfs out t scdv t scde t scdh t scdd t tde t tdv t rdv ( multichannel mode, frame delay 0 {mfd = 0} ) figure 44. serial ports
adsp-21xx rev. b C51C pga pin number name l2 a5 k2 a6 l3 gnd k3 a7 l4 a8 k4 a9 l5 a10 k5 a11 l6 a12 k6 a13 l7 pms k7 dms l8 bms k8 bg l9 xtal k9 clkin l10 clkout c3 index (nc) pin configurations 68-pin pga pga pin number name a10 d3 b10 d4 a9 d5 b9 d6 a8 d7 b8 d8 a7 d9 b7 d10 a6 d11 b6 gnd a5 d12 b5 d13 a4 d14 b4 d15 a3 d16 b3 d17 a2 d18 pga pin number name b1 gnd b2 d19 c1 d20 c2 d21 d1 d22 d2 d23 e1 v dd e2 mmap f1 br f2 irq2 g1 reset g2 a0 h1 a1 h2 a2 j1 a3 j2 a4 k1 v dd pga package adsp-2101 top view (pins down) l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 irq1 (tfs1) a5 gnd a8 a10 a12 pms bms xtal clk out v dd a6 a7 a9 a11 a13 dms bg rd wr clk in gnd d19 d17 d15 d13 gnd d10 d8 d6 d4 d2 a3 a4 reset a0 br irq2 v dd mmap d22 d23 d20 d21 a1 a2 index (nc) d18 d16 d14 d12 d11 d9 d7 d5 d3 v dd sclk1 tfs0 dt0 gnd rfs0 sclk0 dr0 d1 d0 fo (dt1) irq0 (rfs1) fi (dr1) 1 2 3 4 5 6 7 8 9 10 11 l k j h g f e d c b a pga package adsp-2101 bottom view (pins up) 1 2 3 4 5 6 7 8 9 10 11 irq1 (tfs1) a5 gnd a8 a10 a12 pms bms xtal clk out v dd a6 a7 a9 a11 a13 dms bg rd wr clk in gnd d19 d17 d15 d13 gnd d10 d8 d6 d4 d2 a3 a4 reset a0 br irq2 v dd mmap d22 d23 d20 d21 a1 a2 index (nc) d18 d16 d14 d12 d11 d9 d7 d5 d3 v dd sclk1 tfs0 dt0 gnd rfs0 sclk0 dr0 d1 d0 fo (dt1) irq0 (rfs1) fi (dr1) l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 l k j h g f e d c b a nc = no connect pga pin number name k11 wr k10 rd j11 dt0 j10 tfs0 h11 rfs0 h10 gnd g11 dr0 g10 sclk0 f11 fo (dt1) f10 irq1 (tfs1) e11 irq0 (rfs1) e10 fi (dr1) d11 sclk1 d10 v dd c11 d0 c10 d1 b11 d2
adsp-21xx C52C rev. b plcc pin number name 52 fo (dt1) 53 irq1 (tfs1) 54 irq0 (rfs1) 55 fi (dr1) 56 sclk1 57 v dd 58 d0 59 d1 60 d2 61 d3 62 d4 63 d5 64 d6 65 d7 66 d8 67 d9 68 d10 pin configurations 68-lead plcc plcc pin number name 1 d11 2 gnd 3 d12 4 d13 5 d14 6 d15 7 d16 8 d17 9 d18 10 gnd 11 d19 12 d20 13 d21 14 d22 15 d23 16 v dd 17 mmap plcc pin number name 18 br 19 irq2 20 reset 21 a0 22 a1 23 a2 24 a3 25 a4 26 v dd 27 a5 28 a6 29 gnd 30 a7 31 a8 32 a9 33 a10 34 a11 plcc pin number name 35 a12 36 a13 37 pms 38 dms 39 bms 40 bg 41 xtal 42 clkin 43 clkout 44 wr 45 rd 46 dt0 (nc on adsp-2105) 47 tfs0 (nc on adsp-2105) 48 rfs0 (nc on adsp-2105) 49 gnd 50 dr0 (nc on adsp-2105) 51 sclk0 (nc on adsp-2105) nc = no connect gnd d19 d20 d21 d22 d23 v dd mmap br irq2 reset a0 a1 a2 a3 a4 v dd d18 d17 d16 d15 d14 d13 d12 gnd d11 d10 d9 d8 d7 d6 d5 d4 d3 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 pin 1 identifier d2 d1 d0 v dd sclk1 fi (dr1) irq0 (rfs1) irq1 (tfs1) fo (dt1) sclk0 (nc on adsp-2105) dr0 (nc on adsp-2105) gnd rfs0 (nc on adsp-2105) tfs0 (nc on adsp-2105) dt0 (nc on adsp-2105) rd wr a5 a6 gnd a7 a8 a9 a10 a11 a12 a13 pms dms bms bg xtal clkin clkout plcc package adsp-2101 adsp-2103 adsp-2105 adsp-2115 adsp-2161/62/63/64 top view (pins down)
adsp-21xx rev. b C53C pin configurations 80-lead pqfp 80-lead tqfp pqfp/ tqfp pin number name 1a5 2a6 3 gnd 4 gnd 5a7 6a8 7a9 8 a10 9 a11 10 a12 11 a13 12 pms 13 dms 14 bms 15 bg 16 xtal 17 clkin 18 nc 19 nc 20 nc pqfp/ tqfp pin number name 21 clkout 22 wr 23 rd 24 dt0 25 tfs0 26 rfs0 27 gnd 28 gnd 29 dr0 30 sclk0 31 fo (dt1) 32 irq1 (tfs1) 33 irq0 (rfs1) 34 fi (dr1) 35 sclk1 36 v dd 37 d0 38 d1 39 d2 40 d3 pqfp/ tqfp pin number name 41 nc 42 nc 43 nc 44 d4 45 d5 46 d6 47 d7 48 d8 49 d9 50 d10 51 d11 52 gnd 53 gnd 54 d12 55 d13 56 d14 57 d15 58 d16 59 d17 60 d18 pqfp/ tqfp pin number name 61 gnd 62 gnd 63 d19 64 d20 65 d21 66 d22 67 d23 68 v dd 69 v dd 70 mmap 71 br 72 irq2 73 reset 74 a0 75 a1 76 a2 77 a3 78 a4 79 v dd 80 v dd a5 a6 gnd gnd a7 a8 a9 a10 a11 a12 a13 pms dms bms bg xtal clkin nc nc nc d18 d17 d16 d15 d14 d13 d12 gnd gnd d11 d10 d9 d8 d7 d6 d5 d4 nc nc nc clkout wr rd dt0 tfs0 rfs0 gnd gnd dr0 sclk0 fo (dt1) irq1 (tfs1) irq0 (rfs1) f1 (dr1) sclk1 v dd d0 d1 d2 d3 v dd v dd a4 a3 a2 a1 a0 reset irq2 br mmap v dd v dd d23 d22 d21 d20 d19 gnd gnd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pqfp package adsp-2101 adsp-2103 adsp-2115 adsp-2161/62/63/64 top view (pins down) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 nc = no connect
adsp-21xx C54C rev. b pga pin number name l2 fl2 m1 fl1 n1 v dd n2 d1 m2 d0 n3 d3 m3 d2 n4 d5 m4 d4 n5 d7 m5 d6 n6 d10 m6 d9 l6 d8 n7 d12 m7 d11 l7 gnd n8 d13 m8 d14 l8 d15 n9 d16 m9 d17 n10 d18 m10 d19 n11 d20 m11 d22 pga pin number name n13 d23 n12 d21 m13 mmap m12 gnd l13 br l12 reset k13 pms k12 v dd j13 bms j12 dms h13 bg h12 wr h11 rd g13 a2 g12 a0 g11 a1 f13 a3 f12 a4 f11 a5 e13 gnd e12 a6 d13 a7 d12 a8 c13 a9 c12 a11 pin configurations 100-pin pga pga package adsp-2111 top view (pins down) clk out f1 (d r1) index pin (nc) hd1 hd3 ha1 hd13 hd11 hd8 v dd hd4 hd15 a12 a10 hd2 clk in hd0 hd12 hd10 gnd hd6 hd5 hd14 a13 v dd ha0 d5 d7 d3 d18 d16 d13 d12 d10 d20 d21 d23 d1 v dd d4 d6 d2 d19 d17 d14 d11 d9 d22 gnd mmap d0 fl1 d15 gnd d8 fl2 fl0 v dd sclk1 gnd sclk0 rfso a1 a0 a2 tfs0 dr0 a5 a4 a3 dt0 a6 gnd bmode a8 a7 hmd1 hmd0 hd9 hd7 xtal a11 a9 hsize hwr/ hds reset br pms bms bg dms wr rd irq1 (tfs1) irq0 (rfs1) fo (d t1) hack irq2 hrd / hrw hsel ha2/ ale n m l k j h g f e d c b a 13 12 11 10 9 8 7 5 4 6321 13 12 11 10 9 8 7 5 4 6321 n m l k j h g f e d c b a nc = no connect n m l k j h g f e d c b a 13 12 11 10 9 8 7 5 46 3 2 1 n m l k j h g f e d c b a 13 12 11 10 9 8 7 5 46 3 2 1 13 12 11 10 9 8 7 5 46 3 2 1 pga package adsp-2111 bottom view (pins up) d15 gnd d8 hd9 hd7 xtal a2 a3 gnd a7 a9 br pms bms bg reset v dd a0 a4 a6 a8 a11 dms wr a1 a5 rd fo (d t1) hack f1 (dr1) fl0 sclk0 dt0 hmd0 irq1 (tfs1) irq2 clk out d12 d5 d7 d3 d18 d16 d20 d13 d10 d23 d21 v dd d1 d4 d6 d2 d19 d17 d11 d22 d14 d9 mmap gnd fl1 d0 fl2 sclk1 gnd rfso dr0 tfs0 bmode hmd1 irq0 (rfs1) index pin (nc) hsize hrd/ hrw hd1 hd3 v dd hd11 hd13 hd15 hd8 hd4 a10 a12 hwr/ hds hsel ha1 hd2 clk in hd10 hd6 hd12 hd14 gnd hd5 v dd a13 ha0 ha2 / ale hd0 pga pin number name c3 index (nc) a2 ha2/ale a1 ha0 b1 hwr/ hds b2 hsel c1 hsize c2 hrd/hrw d1 hmd0 d2 hmd1 e1 irq2 e2 bmode f1 dt0 f2 clkout f3 hack g1 dr0 g2 tfs0 g3 rfs0 h1 sclk0 h2 gnd h3 fo (dt1) j1 irq1 (tfs1) j2 irq0 (rfs1) k1 fi (dr1) k2 sclk1 l1 fl0 pga pin number name b13 a10 a13 v dd a12 a13 b12 a12 a11 hd14 b11 hd15 a10 hd12 b10 hd13 a9 hd10 b9 hd11 a8 gnd b8 hd8 c8 hd9 a7 hd6 b7 v dd c7 hd7 a6 hd5 b6 hd4 c6 xtal a5 clkin b5 hd3 a4 hd2 b4 hd1 a3 hd0 b3 ha1
adsp-21xx rev. b C55C pin configurations 100-lead bumpered pqfp pqfp pin number name 1 gnd 2 d12 3 d13 4 d14 5 d15 6 d16 7 d17 8 d18 9 d19 10 d20 11 d21 12 d22 13 d23 14 gnd 15 mmap 16 reset 17 br 18 v dd 19 pms 20 dms 21 bms 22 rd 23 wr 24 bg 25 a0 pqfp pin number name 26 a1 27 a2 28 a3 29 a4 30 a5 31 gnd 32 a6 33 a7 34 a8 35 a9 36 a10 37 a11 38 v dd 39 a12 40 a13 41 hd15 42 hd14 43 hd13 44 hd12 45 hd11 46 hd10 47 hd9 48 hd8 49 gnd 50 v dd pqfp pin number name 51 hd7 52 hd6 53 hd5 54 hd4 55 xtal 56 clkin 57 hd3 58 hd2 59 hd1 60 hd0 61 ha2/ale 62 ha1 63 ha0 64 hsel 65 hwr/ hds 66 hrd/hrw 67 hsize 68 hmd1 69 hmd0 70 bmode 71 irq2 72 hack 73 clkout 74 dt0 75 tfs0 pqfp pin number name 76 rfs0 77 dr0 78 sclk0 79 gnd 80 fo (dt1) 81 irq1 (tfs1) 82 irq0 (rfs1) 83 fi (dr1) 84 sclk1 85 fl0 86 fl1 87 fl2 88 v dd 89 d0 90 d1 91 d2 92 d3 93 d4 94 d5 95 d6 96 d7 97 d8 98 d9 99 d10 100 d11 a12 a13 hd15 hd14 hd13 hd12 hd11 hd10 hd9 hd8 gnd vdd hd7 hd6 hd5 hd4 xtal clkin hd3 hd2 hd1 hd0 ha2/ale ha1 ha0 note: pin 1 is located at the center of the beveled-edge side of the package. d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 gnd d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 beveled edge 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 pqfp package adsp-2111 top view (pins down) gnd mmap reset br pms dms bms rd wr bg a0 a1 a2 a3 a4 a5 gnd a6 a7 a8 a9 a10 a11 vdd v dd vdd fl2 fl1 fl0 sclk1 fi (dr1) irq0 (rfs1) irq1 (tfs1) fo (dt1) gnd sclk0 dr0 rfs0 tfs0 dt0 clkout hack irq2 bmode hmd0 hmd1 hsize hrd /hrw hwr / hds hsel
adsp-21xx C56C rev. b inches millimeters symbol min typ max min typ max a 0.123 0.164 3.12 4.17 a 1 0.50 1.27 f b 0.016 0.018 0.020 0.46 f b 1 0.050 1.27 d 1.086 1.110 27.58 28.19 e 1 0.988 1.012 25.10 25.70 e 2 0.788 0.812 20.02 20.62 e 0.100 2.54 l 3 0.180 4.57 outline dimensions adsp-2101 68-pin grid array (pga) a b c d e f g h j k l 1 2 3 4 5 6 7 8 9 10 11 top view guide pin only d b 1 f e d a seating plane l 3 b f a 1 e 1 e 2 e 1 e 2 pga location a1 quadrant marking
adsp-21xx rev. b C57C outline dimensions adsp-21xx 68-lead plastic leaded chip carrier (plcc) inches millimeters symbol min typ max min typ max a 0.169 0.172 0.175 4.29 1 4.37 4.45 a 1 0.104 1 2.64 b 0.017 0.018 0.019 0.43 1 0.46 0.48 b 1 0.027 0.028 0.029 0.69 1 0.71 0.74 d 0.985 0.990 0.995 25.02 25.15 25.27 d 1 0.950 0.952 0.954 24.13 24.18 24.23 d 2 0.895 0.910 0.925 22.73 23.11 23.50 e 0.050 1 1.27 0.004 1 0.10 d e b b 1 a 1 a pin 1 identifier top view (pins down) 9 61 d 1 d bottom view (pins up) d 2 d
adsp-21xx C58C rev. b millimeters inches symbol min typ max min typ max a 2.45 0.096 a 1 0.25 0.010 a 2 1.90 2.00 2.10 0.075 0.079 0.083 d, e 16.95 17.20 17.45 0.667 0.678 0.690 d 1 , e 1 13.90 14.00 14.10 0.547 0.551 0.555 d 3 , e 3 12.35 12.43 0.486 0.490 l 0.65 0.80 0.95 0.026 0.031 0.037 e 0.57 0.65 0.73 0.023 0.026 0.029 b 0.22 0.30 0.38 0.009 0.012 0.015 0.10 0.004 outline dimensions adsp-21xx 80-lead metric plastic quad flatpack (pqfp) 80-lead metric thin quad flatpack (tqfp) millimeters inches min typ max min typ max 1.60 0.063 0.05 0.15 0.002 0.006 1.35 1.40 1.45 0.053 0.055 0.057 15.75 16.00 16.25 0.620 0.630 0.640 13.95 14.00 14.05 0.549 0.551 0.553 12.35 12.43 0.486 0.490 0.50 0.60 0.75 0.020 0.024 0.030 0.57 0.65 0.73 0.022 0.026 0.029 0.25 0.30 0.35 0.010 0.012 0.014 0.10 0.004 d pqfp tqfp 1 80 61 60 41 40 21 20 e e top view (pins down) b e 1 d 1 d e 3 d 3 a l a 1 a 2 seating plane d
adsp-21xx rev. b C59C inches millimeters symbol min typ max min typ max a 0.123 0.169 3.12 4.29 a 1 0.050 1.27 f b 0.016 0.018 0.020 0.41 0.46 0.51 f b 1 0.050 1.27 d 1.308 1.32 1.342 33.22 33.53 34.09 e 1 1.188 1.20 1.212 30.18 30.48 30.78 e 2 0.988 1.00 1.012 25.10 25.4 25.70 e 0.100 2.54 l 3 0.180 4.57 outline dimensions adsp-2111 100-pin grid array (pga) top view index pin only 1 2 3 4 5 6 7 8 9 10 11 13 12 a b c d e f g h j k l nm e 1 e 2 e 1 e 2 seating plane d d a f b e a 1 l 3 f b 1 pga location a1 quadrant marking
adsp-21xx C60C rev. b outline dimensions inches millimeters symbol min typ max min typ max a 0.180 4.572 a 1 0.020 0.030 0.040 0.508 0.762 1.016 a 2 0.130 0.140 0.150 3.302 3.556 3.810 d, e 0.875 0.880 0.885 22.225 22.352 22.479 d 1 , e 1 0.747 0.750 0.753 18.974 19.050 19.126 d 2 , e 2 0.897 0.900 0.903 22.784 22.860 22.936 d 3 , e 3 0.600 0.603 15.240 15.316 l 0.036 0.046 0.914 1.168 e 0.022 0.025 0.028 0.559 0.635 0.711 b 0.008 0.012 0.203 0.305 0.004 0.102 adsp-2111 100-lead bumpered plastic quad flatpack (pqfp) d 13 top view (pins down) 1 e e 1 e 2 e 88 64 39 63 14 38 89 b beveled edge d 1 d d 2 d a 2 a 1 a seating plane l d 3 , e 3 note: pin 1 is the center pin on the beveled-edge side of the package.
adsp-21xx rev. b C61C ordering guide ambient temperature instruction package package part number 1 range rate (mhz) description option adsp-2101kg-66 0 c to +70 c 16.67 mhz 68-pin pga g-68a adsp-2101bg-66 C40 c to +85 c 16.67 mhz 68-pin pga g-68a adsp-2101kp-66 0 c to +70 c 16.67 mhz 68-lead plcc p-68a adsp-2101bp-66 C40 c to +85 c 16.67 mhz 68-lead plcc p-68a adsp-2101ks-66 0 c to +70 c 16.67 mhz 80-lead pqfp s-80 adsp-2101bs-66 C40 c to +85 c 16.67 mhz 80-lead pqfp s-80 adsp-2101kg-80 0 c to +70 c 20.0 mhz 68-pin pga g-68a adsp-2101bg-80 C40 c to +85 c 20.0 mhz 68-pin pga g-68a adsp-2101kp-80 0 c to +70 c 20.0 mhz 68-lead plcc p-68a adsp-2101bp-80 C40 c to +85 c 20.0 mhz 68-lead plcc p-68a adsp-2101ks-80 0 c to +70 c 20.0 mhz 80-lead pqfp s-80 adsp-2101bs-80 C40 c to +85 c 20.0 mhz 80-lead pqfp s-80 adsp-2101kp-100 0 c to +70 c 25.0 mhz 68-pin plcc p-68a adsp-2101bp-100 C40 c to +85 c 25.0 mhz 68-pin plcc p-68a adsp-2101ks-100 0 c to +70 c 25.0 mhz 80-lead pqfp s-80 adsp-2101bs-100 C40 c to +85 c 25.0 mhz 80-lead pqfp s-80 adsp-2101kg-100 0 c to +70 c 25.0 mhz 68-lead pga g-68a adsp-2101bg-100 C40 c to +85 c 25.0 mhz 68-lead pga g-68a adsp-2101tg-50 C55 c to +125 c 12.5 mhz 68-pin pga g-68a adsp-2103kp-40 (3.3 v) 0 c to +70 c 10.24 mhz 68-lead plcc p-68a adsp-2103bp-40 (3.3 v) C40 c to +85 c 10.24 mhz 68-lead plcc p-68a adsp-2103ks-40 (3.3 v) 0 c to +70 c 10.24 mhz 80-lead pqfp s-80 adsp-2103bs-40 (3.3 v) C40 c to +85 c 10.24 mhz 80-lead pqfp s-80 adsp-2105kp-55 0 c to +70 c 13.824 mhz 68-lead plcc p-68a adsp-2105bp-55 C40 c to +85 c 13.824 mhz 68-lead plcc p-68a adsp-2105kp-80 0 c to +70 c 20.0 mhz 68-lead plcc p-68a adsp-2105bp-80 C40 c to +85 c 20.0 mhz 68-lead plcc p-68a adsp-2115kp-66 0 c to +70 c 16.67 mhz 68-lead plcc p-68a adsp-2115bp-66 C40 c to +85 c 16.67 mhz 68-lead plcc p-68a adsp-2115ks-66 0 c to +70 c 16.67 mhz 80-lead pqfp s-80 adsp-2115bs-66 C40 c to +85 c 16.67 mhz 80-lead pqfp s-80 adsp-2115kst-66 0 c to +70 c 16.67 mhz 80-lead tqfp st-80 adsp-2115bst-66 C40 c to +85 c 16.67 mhz 80-lead tqfp st-80 adsp-2115kp-80 0 c to +70 c 20.0 mhz 68-lead plcc p-68a adsp-2115bp-80 C40 c to +85 c 20.0 mhz 68-lead plcc p-68a adsp-2115ks-80 0 c to +70 c 20.0 mhz 80-lead pqfp s-80 adsp-2115bs-80 C40 c to +85 c 20.0 mhz 80-lead pqfp s-80 adsp-2115kst-80 0 c to +70 c 20.0 mhz 80-lead tqfp st-80 adsp-2115bst-80 C40 c to +85 c 20.0 mhz 80-lead tqfp st-80 adsp-2115kp-100 0 c to +70 c 25.0 mhz 68-lead plcc p-68a adsp-2115bp-100 C40 c to +85 c 25.0 mhz 68-lead plcc p-68a notes 1 k = commercial temperature range (0 c to +70 c). b = industrial temperature range (C40 c to +85 c). t = extended temperature range (C55 c to +125 c). g = ceramic pga (pin grid array). p = plcc (plastic leaded chip carrier). s = pqfp (plastic quad flatpack). st = tqfp (thin quad flatpack)
adsp-21xx C62C rev. b ordering guide ambient temperature instruction package package part number 1 range rate (mhz) description option adsp-2111kg-52 0 c to +70 c 13.0 mhz 100-pin pga g-100a adsp-2111bg-52 C40 c to +85 c 13.0 mhz 100-pin pga g-100a adsp-2111ks-52 0 c to +70 c 13.0 mhz 100-lead pqfp s-100a adsp-2111bs-52 C40 c to +85 c 13.0 mhz 100-lead pqfp s-100a adsp-2111kg-66 0 c to +70 c 16.67 mhz 100-pin pga g-100a adsp-2111bg-66 C40 c to +85 c 16.67 mhz 100-pin pga g-100a adsp-2111ks-66 0 c to +70 c 16.67 mhz 100-lead pqfp s-100a adsp-2111bs-66 C40 c to +85 c 16.67 mhz 100-lead pqfp s-100a adsp-2111kg-80 0 c to +70 c 20.0 mhz 100-pin pga g-100a adsp-2111bg-80 C40 c to +85 c 20.0 mhz 100-pin pga g-100a adsp-2111ks-80 0 c to +70 c 20.0 mhz 100-lead pqfp s-100a adsp-2111bs-80 C40 c to +85 c 20.0 mhz 100-lead pqfp s-100a adsp-2111tg-52 C55 c to +125 c 13.0 mhz 100-pin pga g-100a adsp-2161kp-66 2 0 c to +70 c 16.67 mhz 68-lead plcc p-68a adsp-2161bp-66 2 C40 c to +85 c 16.67 mhz 68-lead plcc p-68a adsp-2161ks-66 2 0 c to +70 c 16.67 mhz 80-lead pqfp s-80 adsp-2161bs-66 2 C40 c to +85 c 16.67 mhz 80-lead pqfp s-80 adsp-2162kp-40 (3.3 v) 2 0 c to +70 c 10.24 mhz 68-lead plcc p-68a adsp-2162bp-40 (3.3 v) 2 C40 c to +85 c 10.24 mhz 68-lead plcc p-68a adsp-2162ks-40 (3.3 v) 2 0 c to +70 c 10.24 mhz 80-lead pqfp s-80 adsp-2162bs-40 (3.3 v) 2 C40 c to +85 c 10.24 mhz 80-lead pqfp s-80 adsp-2163kp-66 2 0 c to +70 c 16.67 mhz 68-lead plcc p-68a adsp-2163bp-66 2 C40 c to +85 c 16.67 mhz 68-lead plcc p-68a adsp-2163ks-66 2 0 c to +70 c 16.67 mhz 80-lead pqfp s-80 adsp-2163bs-66 2 C40 c to +85 c 16.67 mhz 80-lead pqfp s-80 adsp-2163kp-100 2 0 c to +70 c 25 mhz 68-lead plcc p-68a adsp-2163bp-100 2 C40 c to +85 c 25 mhz 68-lead plcc p-68a adsp-2163ks-100 2 0 c to +70 c 25 mhz 80-lead pqfp s-80 adsp-2163bs-100 2 C40 c to +85 c 25 mhz 80-lead pqfp s-80 adsp-2164kp-40 (3.3 v) 2 0 c to +70 c 10.24 mhz 68-lead plcc p-68a adsp-2164bp-40 (3.3 v) 2 C40 c to +85 c 10.24 mhz 68-lead plcc p-68a adsp-2164ks-40 (3.3 v) 2 0 c to +70 c 10.24 mhz 80-lead pqfp s-80 adsp-2164bs-40 (3.3 v) 2 C40 c to +85 c 10.24 mhz 80-lead pqfp s-80 notes 1 k = commercial temperature range (0 c to +70 c). b = industrial temperature range (C40 c to +85 c). t = extended temperature range (C55 c to +125 c). g = ceramic pga (pin grid array). p = plcc (plastic leaded chip carrier). s = pqfp (plastic quad flatpack). 2 minimum order quantities required. contact factory for further information.
C63C
c1891bC10C2/96 printed in u.s.a. C64C

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